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From: Rob Herring <robh@kernel.org>
To: Dmitry Osipenko <digetx@gmail.com>
Cc: Thierry Reding <thierry.reding@gmail.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-tegra@vger.kernel.org
Subject: Re: [PATCH v1 2/6] dt-bindings: memory: tegra30: emc: Replace core regulator with power domain
Date: Tue, 30 Mar 2021 17:23:04 -0500	[thread overview]
Message-ID: <20210330222304.GA819312@robh.at.kernel.org> (raw)
In-Reply-To: <20210329194602.17049-3-digetx@gmail.com>

On Mon, Mar 29, 2021 at 10:45:58PM +0300, Dmitry Osipenko wrote:
> Power domain fits much better than a voltage regulator in regards to
> a proper hardware description and from a software perspective as well.
> Hence replace the core regulator with the power domain. Note that this
> doesn't affect any existing DTBs because we haven't started to use the
> regulator yet, and thus, it's okay to change it.
> 
> Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
> ---
>  .../bindings/memory-controllers/nvidia,tegra30-emc.yaml    | 7 ++++---
>  1 file changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml
> index 0a2e2c0d0fdd..4a2edb9b8bdc 100644
> --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml
> +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml
> @@ -39,9 +39,10 @@ properties:
>      description:
>        Phandle of the Memory Controller node.
>  
> -  core-supply:
> +  power-domains:
> +    $ref: /schemas/types.yaml#/definitions/phandle

'power-domains' already has a type. We need to know how many (maxItems).

>      description:
> -      Phandle of voltage regulator of the SoC "core" power domain.
> +      Phandle of the SoC "core" power domain.
>  
>    operating-points-v2:
>      description:
> @@ -241,7 +242,7 @@ examples:
>  
>          nvidia,memory-controller = <&mc>;
>          operating-points-v2 = <&dvfs_opp_table>;
> -        core-supply = <&vdd_core>;
> +        power-domains = <&domain>;
>  
>          #interconnect-cells = <0>;
>  
> -- 
> 2.30.2
> 

  reply	other threads:[~2021-03-30 22:23 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-03-29 19:45 [PATCH v1 0/6] NVIDIA Tegra memory improvements Dmitry Osipenko
2021-03-29 19:45 ` [PATCH v1 1/6] dt-bindings: memory: tegra20: emc: Replace core regulator with power domain Dmitry Osipenko
2021-03-29 19:45 ` [PATCH v1 2/6] dt-bindings: memory: tegra30: " Dmitry Osipenko
2021-03-30 22:23   ` Rob Herring [this message]
2021-03-30 22:31     ` Dmitry Osipenko
2021-03-29 19:45 ` [PATCH v1 3/6] dt-bindings: memory: tegra124: " Dmitry Osipenko
2021-03-29 19:46 ` [PATCH v1 4/6] dt-bindings: memory: tegra20: mc: Convert to schema Dmitry Osipenko
2021-03-30  8:37   ` Krzysztof Kozlowski
2021-03-30 15:25     ` Dmitry Osipenko
2021-03-30 13:08   ` Rob Herring
2021-03-30 13:46     ` Rob Herring
2021-03-30 15:25       ` Dmitry Osipenko
2021-03-29 19:46 ` [PATCH v1 5/6] dt-bindings: memory: tegra20: emc: " Dmitry Osipenko
2021-03-30  8:48   ` Krzysztof Kozlowski
2021-03-30 15:29     ` Dmitry Osipenko
2021-03-30 15:56       ` Dmitry Osipenko
2021-03-30 22:33         ` Rob Herring
2021-03-30 15:32     ` Dmitry Osipenko
2021-03-30 22:35       ` Rob Herring
2021-03-30 15:34     ` Dmitry Osipenko
2021-03-29 19:46 ` [PATCH v1 6/6] memory: tegra: Print out info-level once per driver probe Dmitry Osipenko

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