[PATCH RESEND v3 0/3] MediaTek eMMC inline encryption support

[PATCH RESEND v3 0/3] MediaTek eMMC inline encryption support

[Peng Zhou]

Hello,

Mediatek eMMC hardware IP has Inline Crypto Engine (ICE),
we support inline encryption now.

For Inline Crypto Engine (ICE), see:
- https://lore.kernel.org/linux-arm-msm/
20210126001456.382989-2-ebiggers@kernel.org/T/

This patchset supports Mediatek eMMC inline encryption which meets the
upcoming version of the eMMC specification such as v5.1 or v5.2.

Patch 1-2, add crypto property and crypto clock, patch 3, document the
device tree description about crypto clock.

Please noted that there is a special way of on/off crypto hardware IP
in our SoCs, the enable bit must be controlled under ARM highest
security level, that means must in ARM trusted firmware(ATF).

Changed in v3:
- Removed "mmc: Mediatek: enable crypto hardware engine" patch temporarily.
Needs finding a better way for enable crypto hardware IP through ATF, so
remove "mmc: Mediatek: enable crypto hardware engine" patch temporarily,
we could enable it in ATF directly when boot up which will be a workaround
solution. Discussing about this, see: https://lore.kernel.org/linux-mmc/
YE%2Fnfu8vRETYN9dO@gmail.com/T/#t
- We will put the above mentioned patch in a single patch


Peng Zhou (3):
  mmc: Mediatek: add Inline Crypto Engine support
  arm64: dts: Mediatek: MT6779: add mmc node with ICE setting
  dt-bingdings: mmc: Mediatek: add ICE clock

 Documentation/devicetree/bindings/mmc/mtk-sd.yaml |  6 ++++--
 arch/arm64/boot/dts/mediatek/mt6779.dtsi          | 14 ++++++++++++++
 drivers/mmc/host/mtk-sd.c                         | 15 ++++++++++++++-
 3 files changed, 32 insertions(+), 3 deletions(-)

[PATCH RESEND v3 0/3] MediaTek eMMC inline encryption support

[Peng Zhou]

Hello,

Mediatek eMMC hardware IP has Inline Crypto Engine (ICE),
we support inline encryption now.

For Inline Crypto Engine (ICE), see:
- https://lore.kernel.org/linux-arm-msm/
20210126001456.382989-2-ebiggers@kernel.org/T/

This patchset supports Mediatek eMMC inline encryption which meets the
upcoming version of the eMMC specification such as v5.1 or v5.2.

Patch 1-2, add crypto property and crypto clock, patch 3, document the
device tree description about crypto clock.

Please noted that there is a special way of on/off crypto hardware IP
in our SoCs, the enable bit must be controlled under ARM highest
security level, that means must in ARM trusted firmware(ATF).

Changed in v3:
- Removed "mmc: Mediatek: enable crypto hardware engine" patch temporarily.
Needs finding a better way for enable crypto hardware IP through ATF, so
remove "mmc: Mediatek: enable crypto hardware engine" patch temporarily,
we could enable it in ATF directly when boot up which will be a workaround
solution. Discussing about this, see: https://lore.kernel.org/linux-mmc/
YE%2Fnfu8vRETYN9dO@gmail.com/T/#t
- We will put the above mentioned patch in a single patch


Peng Zhou (3):
  mmc: Mediatek: add Inline Crypto Engine support
  arm64: dts: Mediatek: MT6779: add mmc node with ICE setting
  dt-bingdings: mmc: Mediatek: add ICE clock

 Documentation/devicetree/bindings/mmc/mtk-sd.yaml |  6 ++++--
 arch/arm64/boot/dts/mediatek/mt6779.dtsi          | 14 ++++++++++++++
 drivers/mmc/host/mtk-sd.c                         | 15 ++++++++++++++-
 3 files changed, 32 insertions(+), 3 deletions(-)

[PATCH RESEND v3 2/3] arm64: dts: Mediatek: MT6779: add mmc node with ICE setting

[Peng Zhou]

From: Peng Zhou <Peng.Zhou@mediatek.com>

Add mmc node with Inline Crypto Engine (ICE) for Mediatek
eMMC controller on MT6779.

Signed-off-by: Peng Zhou <Peng.Zhou@mediatek.com>
---
 arch/arm64/boot/dts/mediatek/mt6779.dtsi | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/mediatek/mt6779.dtsi b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
index 9bdf5145966c..9246e59fa4a6 100644
--- a/arch/arm64/boot/dts/mediatek/mt6779.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt6779.dtsi
@@ -242,6 +242,20 @@
 			#clock-cells = <1>;
 		};
 
+		mmc0: mmc@11230000 {
+			compatible = "mediatek,mt6779-mmc";
+			reg = <0 0x11230000 0 0x10000>,
+				<0 0x11f50000 0 0x10000>;
+			interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_LOW>;
+			clocks = <&topckgen CLK_TOP_MSDC50_0>,
+				<&infracfg_ao CLK_INFRA_MSDC0>,
+				<&infracfg_ao CLK_INFRA_MSDC0_SCK>,
+				<&infracfg_ao CLK_INFRA_AES_UFSFDE>;
+			clock-names = "source", "hclk", "source_cg",
+				"crypto";
+			status = "disabled";
+		};
+
 		mfgcfg: clock-controller@13fbf000 {
 			compatible = "mediatek,mt6779-mfgcfg", "syscon";
 			reg = <0 0x13fbf000 0 0x1000>;
-- 
2.18.0