From: Vignesh Raghavendra <vigneshr@ti.com>
To: Nishanth Menon <nm@ti.com>, Tero Kristo <kristo@kernel.org>
Cc: "Rob Herring" <robh+dt@kernel.org>,
"Péter Ujfalusi" <peter.ujfalusi@gmail.com>,
"Vignesh Raghavendra" <vigneshr@ti.com>,
linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: [PATCH] arm64: dts: ti: j7200-main: Mark Main NAVSS as dma-coherent
Date: Tue, 27 Apr 2021 23:21:30 +0530 [thread overview]
Message-ID: <20210427175130.29451-1-vigneshr@ti.com> (raw)
Traffic through main NAVSS interconnect is coherent wrt ARM caches on
J7200 SoC. Add missing dma-coherent property to main_navss node.
Also add dma-ranges to be consistent with mcu_navss node.
Fixes: d361ed88455fe ("arm64: dts: ti: Add support for J7200 SoC")
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
---
arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
index f86c493a44f1c..a6826f1888ef0 100644
--- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
@@ -85,6 +85,8 @@ main_navss: bus@30000000 {
#size-cells = <2>;
ranges = <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
ti,sci-dev-id = <199>;
+ dma-coherent;
+ dma-ranges;
main_navss_intr: interrupt-controller1 {
compatible = "ti,sci-intr";
--
2.31.1
next reply other threads:[~2021-04-27 17:52 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-27 17:51 Vignesh Raghavendra [this message]
2021-04-27 18:19 ` [PATCH] arm64: dts: ti: j7200-main: Mark Main NAVSS as dma-coherent Péter Ujfalusi
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