Re: [PATCH v4 1/2] dt-bindings: clk: microchip: Add Microchip PolarFire host binding

[Rob Herring <robh@kernel.org>]

On Wed, Apr 28, 2021 at 01:27:10PM +0100, daire.mcnamara@microchip.com wrote:
> From: Daire McNamara <daire.mcnamara@microchip.com>
> 
> Add device tree bindings for the Microchip PolarFire system
> clock controller
> 
> Signed-off-by: Daire McNamara <daire.mcnamara@microchip.com>
> ---
>  .../bindings/clock/microchip,mpfs.yaml        | 73 +++++++++++++++++++
>  .../dt-bindings/clock/microchip,mpfs-clock.h  | 45 ++++++++++++
>  2 files changed, 118 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/microchip,mpfs.yaml
>  create mode 100644 include/dt-bindings/clock/microchip,mpfs-clock.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml
> new file mode 100644
> index 000000000000..a4756480a8ec
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml
> @@ -0,0 +1,73 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/microchip,mpfs.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Microchip PolarFire Clock Control Module Binding
> +
> +maintainers:
> +  - Daire McNamara <daire.mcnamara@microchip.com>
> +
> +description: |
> +  Microchip PolarFire clock control (CLKCFG) is an integrated clock controller,
> +  which gates and enables all peripheral clocks.
> +
> +  This device tree binding describes 32 gate clocks.  Clocks are referenced by
> +  user nodes by the CLKCFG node phandle and the clock index in the group, from
> +  0 to 31.
> +
> +properties:
> +  compatible:
> +    const: microchip,mpfs-clkcfg
> +
> +  reg:
> +    maxItems: 1
> +
> +  clocks:
> +    maxItems: 1
> +
> +  '#clock-cells':
> +    const: 1
> +    description: |
> +      The clock consumer should specify the desired clock by having the clock
> +      ID in its "clocks" phandle cell. See include/dt-bindings/clock/microchip,mpfs-clock.h
> +      for the full list of PolarFire clock IDs.
> +
> +  clock-output-names:
> +    maxItems: 32
> +
> +required:
> +  - compatible
> +  - reg
> +  - clocks
> +  - '#clock-cells'
> +  - clock-output-names
> +
> +additionalProperties: false
> +
> +examples:
> +  # Clock Config node:
> +  - |
> +    #include <dt-bindings/clock/microchip,mpfs-clock.h>
> +    soc {
> +            #address-cells = <2>;
> +            #size-cells = <2>;
> +            ref: refclk {
> +                compatible = "fixed-clock";
> +                #clock-cells = <0>;
> +                clock-frequency = <600000000>;
> +                clock-output-names = "msspllclk";
> +            };

This belongs at the top level. Or just omit it.

> +            clkcfg: clock-controller@20002000 {
> +                compatible = "microchip,mpfs-clkcfg";
> +                reg = <0x0 0x20002000 0x0 0x1000>;
> +                clocks = <&ref>;
> +                #clock-cells = <1>;
> +                clock-output-names = "cpu", "axi", "ahb", "envm", "mac0", "mac1", "mmc", "timer",
> +                                     "mmuart0", "mmuart1", "mmuart2", "mmuart3", "mmuart4",
> +                                     "spi0", "spi1", "i2c0", "i2c1", "can0", "can1", "usb", "rtc",
> +                                     "qspi", "gpio0", "gpio1", "gpio2", "ddrc",
> +                                     "fic0", "fic1", "fic2", "fic3", "athena", "cfm";
> +        };
> +    };
> diff --git a/include/dt-bindings/clock/microchip,mpfs-clock.h b/include/dt-bindings/clock/microchip,mpfs-clock.h
> new file mode 100644
> index 000000000000..d217b039a873
> --- /dev/null
> +++ b/include/dt-bindings/clock/microchip,mpfs-clock.h
> @@ -0,0 +1,45 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */

Dual license please.

> +/*
> + * Daire McNamara,<daire.mcnamara@microchip.com>
> + * Copyright (C) 2020 Microchip Technology Inc.  All rights reserved.
> + */
> +
> +#ifndef _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_
> +#define _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_
> +
> +#define CLK_CPU	0
> +#define CLK_AXI	1
> +#define CLK_AHB	2
> +
> +#define CLK_ENVM	3
> +#define CLK_MAC0	4
> +#define CLK_MAC1	5
> +#define CLK_MMC	6
> +#define CLK_TIMER	7
> +#define CLK_MMUART0	8
> +#define CLK_MMUART1	9
> +#define CLK_MMUART2	10
> +#define CLK_MMUART3	11
> +#define CLK_MMUART4	12
> +#define CLK_SPI0	13
> +#define CLK_SPI1	14
> +#define CLK_I2C0	15
> +#define CLK_I2C1	16
> +#define CLK_CAN0	17
> +#define CLK_CAN1	18
> +#define CLK_USB	19
> +#define CLK_RESERVED	20
> +#define CLK_RTC	21
> +#define CLK_QSPI	22
> +#define CLK_GPIO0	23
> +#define CLK_GPIO1	24
> +#define CLK_GPIO2	25
> +#define CLK_DDRC	26
> +#define CLK_FIC0	27
> +#define CLK_FIC1	28
> +#define CLK_FIC2	29
> +#define CLK_FIC3	30
> +#define CLK_ATHENA	31
> +#define CLK_CFM	32

I thought it was 0-31 clocks?

> +
> +#endif	/* _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ */
> -- 
> 2.25.1
>