From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-10.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 10C9CC433B4 for ; Thu, 6 May 2021 10:31:09 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C688361177 for ; Thu, 6 May 2021 10:31:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234403AbhEFKcF (ORCPT ); Thu, 6 May 2021 06:32:05 -0400 Received: from foss.arm.com ([217.140.110.172]:60850 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234356AbhEFKcF (ORCPT ); Thu, 6 May 2021 06:32:05 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id C8CC9D6E; Thu, 6 May 2021 03:31:06 -0700 (PDT) Received: from bogus (unknown [10.57.33.10]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1DE1B3F73B; Thu, 6 May 2021 03:31:05 -0700 (PDT) Date: Thu, 6 May 2021 11:31:02 +0100 From: Sudeep Holla To: Michael Kelley Cc: "linux-arm-kernel@lists.infradead.org" , "devicetree@vger.kernel.org" , "arve@google.com" , Andrew Walbran , David Hartley , Achin Gupta , Jens Wiklander , Arunachalam Ganapathy , Marc Bonnici , Will Deacon , Mark Rutland Subject: Re: [PATCH v6 1/6] arm64: smccc: Add support for SMCCCv1.2 extended input/output registers Message-ID: <20210506103102.rarcglpmbqk7yuzd@bogus> References: <20210505093843.3308691-1-sudeep.holla@arm.com> <20210505093843.3308691-2-sudeep.holla@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: User-Agent: NeoMutt/20171215 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Michael, On Wed, May 05, 2021 at 03:28:56PM +0000, Michael Kelley wrote: > From: Sudeep Holla Sent: Wednesday, May 5, 2021 2:39 AM > > > > SMCCC v1.2 allows x8-x17 to be used as parameter registers and x4—x17 > > to be used as result registers in SMC64/HVC64. Arm Firmware Framework > > for Armv8-A specification makes use of x0-x7 as parameter and result > > registers. There are other users like Hyper-V who intend to use beyond > > x0-x7 as well. > > > > Current SMCCC interface in the kernel just use x0-x7 as parameter and > > x0-x3 as result registers as required by SMCCCv1.0. Let us add new > > interface to support this extended set of input/output registers namely > > x0-x17 as both parameter and result registers. > > [...] > I've tested the new arm_smccc_1_2_hvc() function in the context > of Linux guests making hypercalls on Hyper-V for ARM64, and it > works as intended. But note that my test case only uses X0 thru X7. > > Tested-by: Michael Kelley > Reviewed-by: Michael Kelley Thanks! -- Regards, Sudeep