From: Rob Herring <robh@kernel.org>
To: Sergio Paracuellos <sergio.paracuellos@gmail.com>
Cc: vkoul@kernel.org, linux-phy@lists.infradead.org, kishon@ti.com,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-staging@lists.linux.dev, gregkh@linuxfoundation.org,
neil@brown.name, ilya.lipnitskiy@gmail.com
Subject: Re: [PATCH 2/5] dt-bindings: phy: mediatek,mt7621-pci-phy: add clock entries
Date: Fri, 7 May 2021 17:12:00 -0500 [thread overview]
Message-ID: <20210507221200.GA2984128@robh.at.kernel.org> (raw)
In-Reply-To: <20210506111531.21978-3-sergio.paracuellos@gmail.com>
On Thu, May 06, 2021 at 01:15:28PM +0200, Sergio Paracuellos wrote:
> MT7621 SoC clock driver has already mainlined in
> 'commit 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC")'
> Hence update schema with the add of the entries related to
> clock.
>
> Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
> ---
> .../bindings/phy/mediatek,mt7621-pci-phy.yaml | 12 ++++++++++++
> 1 file changed, 12 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml b/Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml
> index 0ccaded3f245..d8614ef8995c 100644
> --- a/Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/mediatek,mt7621-pci-phy.yaml
> @@ -16,6 +16,14 @@ properties:
> reg:
> maxItems: 1
>
> + clocks:
> + maxItems: 1
> + description:
> + PHY reference clock. Must contain an entry in clock-names.
> +
> + clock-names:
> + const: sys_clk
You don't really need -names when there is only 1.
> +
> "#phy-cells":
> const: 1
> description: selects if the phy is dual-ported
> @@ -23,6 +31,8 @@ properties:
> required:
> - compatible
> - reg
> + - clocks
> + - clock-names
Technically, you can't add new properties and make them required as that
breaks the ABI. If that's okay here, explain it in the commit message.
> - "#phy-cells"
>
> additionalProperties: false
> @@ -32,5 +42,7 @@ examples:
> pcie0_phy: pcie-phy@1e149000 {
> compatible = "mediatek,mt7621-pci-phy";
> reg = <0x1e149000 0x0700>;
> + clocks = <&sysc 0>;
> + clock-names = "sys_clk";
> #phy-cells = <1>;
> };
> --
> 2.25.1
>
next prev parent reply other threads:[~2021-05-07 22:12 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-06 11:15 [PATCH 0/5] phy: ralink: mt7621-pci-phy: some improvements Sergio Paracuellos
2021-05-06 11:15 ` [PATCH 1/5] staging: mt7621-dts: use clock in pci phy nodes Sergio Paracuellos
2021-05-06 11:15 ` [PATCH 2/5] dt-bindings: phy: mediatek,mt7621-pci-phy: add clock entries Sergio Paracuellos
2021-05-07 22:12 ` Rob Herring [this message]
2021-05-08 6:40 ` Sergio Paracuellos
2021-05-06 11:15 ` [PATCH 3/5] phy: ralink: phy-mt7621-pci: use kernel clock APIS Sergio Paracuellos
2021-05-06 11:15 ` [PATCH 4/5] phy: ralink: Kconfig: enable COMPILE_TEST on mt7621-pci-phy driver Sergio Paracuellos
2021-05-06 15:59 ` kernel test robot
2021-05-07 6:13 ` Sergio Paracuellos
2021-05-06 11:15 ` [PATCH 5/5] phy: ralink: Kconfig: convert mt7621-pci-phy into 'bool' Sergio Paracuellos
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