From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
To: vkoul@kernel.org
Cc: kishon@ti.com, devicetree@vger.kernel.org,
linux-phy@lists.infradead.org, robh+dt@kernel.org,
linux-staging@lists.linux.dev, gregkh@linuxfoundation.org,
neil@brown.name, ilya.lipnitskiy@gmail.com
Subject: [PATCH RESEND v2 1/6] staging: mt7621-dts: use clock in pci phy nodes
Date: Sat, 8 May 2021 09:09:25 +0200 [thread overview]
Message-ID: <20210508070930.5290-2-sergio.paracuellos@gmail.com> (raw)
In-Reply-To: <20210508070930.5290-1-sergio.paracuellos@gmail.com>
MT7621 SoC clock driver has already mainlined in
'commit 48df7a26f470 ("clk: ralink: add clock driver for mt7621 SoC")'
Hence we can use the clock in pcie phy nodes to
be able to get it from there in driver code.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
drivers/staging/mt7621-dts/mt7621.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/staging/mt7621-dts/mt7621.dtsi b/drivers/staging/mt7621-dts/mt7621.dtsi
index 9ee11adefa79..840ba0c3ffed 100644
--- a/drivers/staging/mt7621-dts/mt7621.dtsi
+++ b/drivers/staging/mt7621-dts/mt7621.dtsi
@@ -548,12 +548,14 @@ pcie@2,0 {
pcie0_phy: pcie-phy@1e149000 {
compatible = "mediatek,mt7621-pci-phy";
reg = <0x1e149000 0x0700>;
+ clocks = <&sysc MT7621_CLK_XTAL>;
#phy-cells = <1>;
};
pcie2_phy: pcie-phy@1e14a000 {
compatible = "mediatek,mt7621-pci-phy";
reg = <0x1e14a000 0x0700>;
+ clocks = <&sysc MT7621_CLK_XTAL>;
#phy-cells = <1>;
};
};
--
2.25.1
next prev parent reply other threads:[~2021-05-08 7:09 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-08 7:09 [PATCH RESEND v2 0/6] phy: ralink: mt7621-pci-phy: some improvements Sergio Paracuellos
2021-05-08 7:09 ` Sergio Paracuellos [this message]
2021-05-08 7:09 ` [PATCH RESEND v2 2/6] dt-bindings: phy: mediatek,mt7621-pci-phy: add clock entries Sergio Paracuellos
2021-05-10 16:01 ` Rob Herring
2021-05-08 7:09 ` [PATCH RESEND v2 3/6] phy: ralink: phy-mt7621-pci: use kernel clock APIS Sergio Paracuellos
2021-05-08 7:09 ` [PATCH RESEND v2 4/6] phy: ralink: Kconfig: enable COMPILE_TEST on mt7621-pci-phy driver Sergio Paracuellos
2021-05-08 7:09 ` [PATCH RESEND v2 5/6] phy: ralink: Kconfig: convert mt7621-pci-phy into 'bool' Sergio Paracuellos
2021-05-08 7:09 ` [PATCH RESEND v2 6/6] phy: ralink: phy-mt7621-pci: properly print pointer address Sergio Paracuellos
2021-05-14 10:46 ` [PATCH RESEND v2 0/6] phy: ralink: mt7621-pci-phy: some improvements Vinod Koul
2021-05-14 11:19 ` Sergio Paracuellos
2021-05-14 11:22 ` Greg KH
2021-05-14 11:30 ` Sergio Paracuellos
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