From: Rob Herring <robh@kernel.org>
To: Linus Walleij <linus.walleij@linaro.org>
Cc: linux-crypto@vger.kernel.org,
Herbert Xu <herbert@gondor.apana.org.au>,
"David S . Miller" <davem@davemloft.net>,
linux-arm-kernel@lists.infradead.org,
Imre Kaloz <kaloz@openwrt.org>,
Krzysztof Halasa <khalasa@piap.pl>, Arnd Bergmann <arnd@arndb.de>,
devicetree@vger.kernel.org
Subject: Re: [PATCH 2/3] crypto: ixp4xx: Add DT bindings
Date: Tue, 11 May 2021 11:16:48 -0500 [thread overview]
Message-ID: <20210511161648.GA2209918@robh.at.kernel.org> (raw)
In-Reply-To: <20210510213634.600866-2-linus.walleij@linaro.org>
On Mon, May 10, 2021 at 11:36:33PM +0200, Linus Walleij wrote:
> This adds device tree bindings for the ixp4xx crypto engine.
>
> Cc: devicetree@vger.kernel.org
> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
> ---
> Herbert, David: This can be applied separately once we are
> happy with the bindings, alternatively it can be merged
> with the support code into ARM SoC.
> ---
> .../bindings/crypto/intel,ixp4xx-crypto.yaml | 59 +++++++++++++++++++
> 1 file changed, 59 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml
>
> diff --git a/Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml b/Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml
> new file mode 100644
> index 000000000000..28d75f4f9a76
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/crypto/intel,ixp4xx-crypto.yaml
> @@ -0,0 +1,59 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +# Copyright 2018 Linaro Ltd.
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/crypto/intel,ixp4xx-crypto.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Intel IXP4xx cryptographic engine
> +
> +maintainers:
> + - Linus Walleij <linus.walleij@linaro.org>
> +
> +description: |
> + The Intel IXP4xx cryptographic engine makes use of the IXP4xx NPE
> + (Network Processing Engine). Since it is not a device on its own
> + it is defined as a subnode of the NPE, if crypto support is
> + available on the platform.
> +
> +properties:
> + compatible:
> + const: intel,ixp4xx-crypto
> +
> + intel,npe-handle:
> + $ref: '/schemas/types.yaml#/definitions/phandle-array'
> + maxItems: 1
> + description: phandle to the NPE this ethernet instance is using
> + and the instance to use in the second cell
> +
> + queue-rx:
> + $ref: '/schemas/types.yaml#/definitions/phandle-array'
> + maxItems: 1
> + description: phandle to the RX queue on the NPE
> +
> + queue-txready:
> + $ref: '/schemas/types.yaml#/definitions/phandle-array'
> + maxItems: 1
> + description: phandle to the TX READY queue on the NPE
> +
> +required:
> + - compatible
> + - intel,npe-handle
> + - queue-rx
> + - queue-txready
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + npe: npe@c8006000 {
> + compatible = "intel,ixp4xx-network-processing-engine";
> + reg = <0xc8006000 0x1000>, <0xc8007000 0x1000>, <0xc8008000 0x1000>;
> +
> + crypto {
The parent schema needs to define 'crypto' and have a ref to this
schema. I'd put the example there rather than piecemeal.
> + compatible = "intel,ixp4xx-crypto";
> + intel,npe-handle = <&npe 2>;
A bit redundant to have a phandle to the parent.
> + queue-rx = <&qmgr 30>;
> + queue-txready = <&qmgr 29>;
> + };
> + };
> --
> 2.30.2
>
prev parent reply other threads:[~2021-05-12 20:55 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20210510213634.600866-1-linus.walleij@linaro.org>
2021-05-10 21:36 ` [PATCH 2/3] crypto: ixp4xx: Add DT bindings Linus Walleij
2021-05-11 13:40 ` Rob Herring
2021-05-11 16:16 ` Rob Herring [this message]
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