From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.3 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C9D05C4708A for ; Thu, 27 May 2021 04:02:29 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A2D63613D1 for ; Thu, 27 May 2021 04:02:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229657AbhE0EEA (ORCPT ); Thu, 27 May 2021 00:04:00 -0400 Received: from twspam01.aspeedtech.com ([211.20.114.71]:57208 "EHLO twspam01.aspeedtech.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229453AbhE0EEA (ORCPT ); Thu, 27 May 2021 00:04:00 -0400 Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 14R3moGk084120; Thu, 27 May 2021 11:48:50 +0800 (GMT-8) (envelope-from steven_lee@aspeedtech.com) Received: from aspeedtech.com (192.168.100.253) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Thu, 27 May 2021 12:01:53 +0800 Date: Thu, 27 May 2021 12:01:47 +0800 From: Steven Lee To: Andrew Jeffery CC: Linus Walleij , Bartosz Golaszewski , Rob Herring , Joel Stanley , "open list:GPIO SUBSYSTEM" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "moderated list:ARM/ASPEED MACHINE SUPPORT" , "moderated list:ARM/ASPEED MACHINE SUPPORT" , open list , Hongwei Zhang , Ryan Chen , Billy Tsai Subject: Re: [PATCH v1 2/4] ARM: dts: aspeed-g6: Add SGPIO node. Message-ID: <20210527040146.GE9971@aspeedtech.com> References: <20210526094609.14068-1-steven_lee@aspeedtech.com> <20210526094609.14068-3-steven_lee@aspeedtech.com> <69b31043-957c-40af-9ab9-6bcc63ccdc85@www.fastmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Disposition: inline In-Reply-To: <69b31043-957c-40af-9ab9-6bcc63ccdc85@www.fastmail.com> User-Agent: Mutt/1.9.4 (2018-02-28) X-Originating-IP: [192.168.100.253] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 14R3moGk084120 Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org The 05/27/2021 09:27, Andrew Jeffery wrote: > Hi Steven, > > On Wed, 26 May 2021, at 19:16, Steven Lee wrote: > > AST2600 supports 2 SGPIO master interfaces one with 128 pins another one > > with 80 pins. > > Is there any chance the serial GPIO controllers can be explicitly > listed in the Memory Space Allocation Table of the datasheet? Currently > they're covered by the entry for "GPIO Controller (Parallel GPIO)" > which is listed as ranging from 0x1e780000-0x1e7807ff. > I've forwarded your suggestion to designers. Per the discussion with designers, they may change the GPIO controller description of Memory Space Allocation Table to "GPIO Controller (including Parallel and Serial GPIO)". > Admittedly the details are listed in chapter 41 for the GPIO > Controller, but it would be handy to not have to dig. > > > > > Signed-off-by: Steven Lee > > --- > > arch/arm/boot/dts/aspeed-g6.dtsi | 32 ++++++++++++++++++++++++++++++++ > > 1 file changed, 32 insertions(+) > > > > diff --git a/arch/arm/boot/dts/aspeed-g6.dtsi b/arch/arm/boot/dts/aspeed-g6.dtsi > > index f96607b7b4e2..556ce9535c22 100644 > > --- a/arch/arm/boot/dts/aspeed-g6.dtsi > > +++ b/arch/arm/boot/dts/aspeed-g6.dtsi > > @@ -377,6 +377,38 @@ > > #interrupt-cells = <2>; > > }; > > > > + sgpiom0: sgpiom@1e780500 { > > + #gpio-cells = <2>; > > + gpio-controller; > > + compatible = "aspeed,ast2600-sgpiom"; > > + reg = <0x1e780500 0x100>; > > + interrupts = ; > > + max-ngpios = <128>; > > I need to think more about this one. > > Andrew