From: Rob Herring <robh@kernel.org>
To: Martin Botka <martin.botka@somainline.org>
Cc: ~postmarketos/upstreaming@lists.sr.ht,
konrad.dybcio@somainline.org,
angelogioacchino.delregno@somainline.org,
marijn.suijten@somainline.org, jamipkettunen@somainline.org,
Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH V3 1/2] dt-bindings: clk: qcom: gcc-sm6125: Document SM6125 GCC driver
Date: Wed, 2 Jun 2021 14:08:41 -0500 [thread overview]
Message-ID: <20210602190841.GA3792989@robh.at.kernel.org> (raw)
In-Reply-To: <20210526184325.675736-1-martin.botka@somainline.org>
On Wed, May 26, 2021 at 08:43:20PM +0200, Martin Botka wrote:
> Document the newly added SM6125 GCC driver.
>
> Signed-off-by: Martin Botka <martin.botka@somainline.org>
> ---
> Changes in V2:
> Add commit description.
> Changes in V3:
> Use rpmcc.h instead of rpmh.h
> .../bindings/clock/qcom,gcc-sm6125.yaml | 72 +++++++++++++++++++
> 1 file changed, 72 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml
> new file mode 100644
> index 000000000000..f7198370a1b9
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-sm6125.yaml
> @@ -0,0 +1,72 @@
> +# SPDX-License-Identifier: GPL-2.0-only
Dual license new bindings please:
GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/qcom,gcc-sm6125.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Qualcomm Global Clock & Reset Controller Binding for SM6125
> +
> +maintainers:
> + - Konrad Dybcio <konrad.dybcio@somainline.org>
> +
> +description: |
> + Qualcomm global clock control module which supports the clocks, resets and
> + power domains on SM6125.
> +
> + See also:
> + - dt-bindings/clock/qcom,gcc-sm6125.h
> +
> +properties:
> + compatible:
> + const: qcom,gcc-sm6125
The normal ordering would be 'qcom,sm6125-gcc'
> +
> + clocks:
> + items:
> + - description: Board XO source
> + - description: Sleep clock source
> +
> + clock-names:
> + items:
> + - const: bi_tcxo
> + - const: sleep_clk
> +
> + '#clock-cells':
> + const: 1
> +
> + '#reset-cells':
> + const: 1
> +
> + '#power-domain-cells':
> + const: 1
> +
> + reg:
> + maxItems: 1
> +
> + protected-clocks:
> + description:
> + Protected clock specifier list as per common clock binding.
> +
> +required:
> + - compatible
> + - clocks
> + - clock-names
> + - reg
> + - '#clock-cells'
> + - '#reset-cells'
> + - '#power-domain-cells'
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,rpmcc.h>
> + clock-controller@1400000 {
> + compatible = "qcom,gcc-sm6125";
Wrong indentation.
> + reg = <0x01400000 0x1f0000>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> + #power-domain-cells = <1>;
> + clock-names = "bi_tcxo", "sleep_clk";
> + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&sleep_clk>;
> + };
> +...
> --
> 2.31.1
next prev parent reply other threads:[~2021-06-02 19:08 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-05-26 18:43 [PATCH V3 1/2] dt-bindings: clk: qcom: gcc-sm6125: Document SM6125 GCC driver Martin Botka
2021-05-26 18:43 ` [PATCH V3 2/2] clk: qcom: Add SM6125 (TRINKET) " Martin Botka
2021-06-02 19:10 ` Rob Herring
2021-06-02 19:08 ` Rob Herring [this message]
2021-06-05 10:56 ` [PATCH V3 1/2] dt-bindings: clk: qcom: gcc-sm6125: Document SM6125 " Konrad Dybcio
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