Re: [PATCH V2 2/2] arm64: dts: ti: Add support for J721E EAIK

Nishanth Menon
2021-06-07T13:35:37Z

On 15:03-20210607, Sinthu Raja wrote:
> From: Sinthu Raja <sinthu.raja@ti.com>
>
> J721E EdgeAI Kit (EAIK) is a low cost, small form factor board designed
> for TI’s J721E SoC. TI’s J721E SoC comprises of dual core A72, high
> performance vision accelerators, video codec accelerators, latest C71x
> and C66x DSP, high bandwidth real-time IPs for capture and display, GPU,
> dedicated safety island and security accelerators. The SoC is power
> optimized to provide best in class performance for perception, sensor
> fusion, localization, path planning tasks in robotics, industrial and
> automotive applications.
>
> J721E EAIK supports the following interfaces:
> * 4 GB LPDDR4 RAM
> * x1 Gigabit Ethernet interface
> * x1 USB 3.0 Type-C port
> * x3 USB 3.0 Type-A ports
> * x1 UHS-1 capable µSD card slot
> * x1 PCIe M.2 E Key with x1 USB2.0, x1 MCASP, x1 MMC, x1 UART
> * x1 PCIe M.2 M Key
> * 512 Mbit OSPI flash
> * x4 UART through UART-USB bridge
> * x4 CAN-FD interface
> * x1 DP interface
> * x1 HDMI interface
> * x2 CSI2 Camera interface (RPi and TI Camera connector)
> * 40-pin Raspberry Pi compatible GPIO header
> * Compact TI 20-Pin connector for JTAG debug
> * Interface for remote automation. Includes:
> * power measurement and reset control
> * boot mode change

please reduce the description above, also add a url for the board.
>
> Add basic support for J721E-EAIK.
>
> Signed-off-by: Amarnath MB <amarnath.mb@ti.com>
> Signed-off-by: Sinthu Raja <sinthu.raja@ti.com>
> ---
> arch/arm64/boot/dts/ti/Makefile | 2 +
> arch/arm64/boot/dts/ti/k3-j721e-eaik.dts | 342 +++++++++++++++++++++++
> 2 files changed, 344 insertions(+)
> create mode 100644 arch/arm64/boot/dts/ti/k3-j721e-eaik.dts
>
> diff --git a/arch/arm64/boot/dts/ti/Makefile b/arch/arm64/boot/dts/ti/Makefile
> index d56c742f5a10..00eb2077616e 100644
> --- a/arch/arm64/boot/dts/ti/Makefile
> +++ b/arch/arm64/boot/dts/ti/Makefile
> @@ -12,6 +12,8 @@ dtb-$(CONFIG_ARCH_K3) += k3-am6548-iot2050-advanced.dtb
>
> dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board.dtb
>
> +dtb-$(CONFIG_ARCH_K3) += k3-j721e-eaik.dtb

Keep the above two together:
dtb-$(CONFIG_ARCH_K3) += k3-j721e-common-proc-board.dtb
dtb-$(CONFIG_ARCH_K3) += k3-j721e-eaik.dtb

> +
> dtb-$(CONFIG_ARCH_K3) += k3-j7200-common-proc-board.dtb
>
> dtb-$(CONFIG_ARCH_K3) += k3-am642-evm.dtb
> diff --git a/arch/arm64/boot/dts/ti/k3-j721e-eaik.dts b/arch/arm64/boot/dts/ti/k3-j721e-eaik.dts
> new file mode 100644
> index 000000000000..decb16274333
> --- /dev/null
> +++ b/arch/arm64/boot/dts/ti/k3-j721e-eaik.dts
> @@ -0,0 +1,342 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
> + */
> +
> +/dts-v1/;
> +
> +#include "k3-j721e.dtsi"
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/input/input.h>
> +#include <dt-bindings/net/ti-dp83867.h>
> +
> +/ {
> + compatible = "ti,j721e-eaik", "ti,j721e";
> + model = "Texas Instruments J721E EAIK";
> +
> + chosen {
> + stdout-path = "serial2:115200n8";
> + bootargs = "console=ttyS2,115200n8 earlycon=ns16550a,mmio32,0x02800000";
> + };
> +
> + memory@80000000 {
> + device_type = "memory";
> + /* 4G RAM */
> + reg = <0x00000000 0x80000000 0x00000000 0x80000000>,
> + <0x00000008 0x80000000 0x00000000 0x80000000>;
> + };
> +
> + reserved_memory: reserved-memory {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> +
> + secure_ddr: optee@9e800000 {
> + reg = <0x00 0x9e800000 0x00 0x01800000>;
> + alignment = <0x1000>;
> + no-map;
> + };
> + };
> +
> + vusb_main: fixedregulator-vusb-main5v0 {
> + /* USB MAIN INPUT 5V DC */
> + compatible = "regulator-fixed";
> + regulator-name = "vusb-main5v0";
> + regulator-min-microvolt = <5000000>;
> + regulator-max-microvolt = <5000000>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + vsys_3v3: fixedregulator-vsys3v3 {
> + /* Output of LM5141 */
> + compatible = "regulator-fixed";
> + regulator-name = "vsys_3v3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + vin-supply = <&vusb_main>;
> + regulator-always-on;
> + regulator-boot-on;
> + };
> +
> + vdd_mmc1: fixedregulator-sd {
> + compatible = "regulator-fixed";
> + pinctrl-names = "default";
> + pinctrl-0 = <&vdd_mmc1_en_pins_default>;
> + regulator-name = "vdd_mmc1";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + enable-active-high;
> + vin-supply = <&vsys_3v3>;
> + gpio = <&wkup_gpio0 8 GPIO_ACTIVE_HIGH>;
> + };
> +
> + vdd_sd_dv_alt: gpio-regulator-tps659411 {
> + compatible = "regulator-gpio";
> + pinctrl-names = "default";
> + pinctrl-0 = <&vdd_sd_dv_alt_pins_default>;
> + regulator-name = "tps659411";
> + regulator-min-microvolt = <1800000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-boot-on;
> + vin-supply = <&vsys_3v3>;
> + gpios = <&wkup_gpio0 9 GPIO_ACTIVE_HIGH>;
> + states = <1800000 0x0>,
> + <3300000 0x1>;
> + };
> +};
> +
> +&main_pmx0 {
> + main_mmc1_pins_default: main-mmc1-pins-default {
> + pinctrl-single,pins = <
> + J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
> + J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
> + J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
> + J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
> + J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
> + J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
> + J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
> + J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
> + >;
> + };
> +
> + main_uart0_pins_default: main-uart0-pins-default {
> + pinctrl-single,pins = <
> + J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */
> + J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */
> + J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
> + J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
> + >;
> + };
> +
> + main_i2c0_pins_default: main-i2c0-pins-default {
> + pinctrl-single,pins = <
> + J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
> + J721E_IOPAD(0x224, PIN_INPUT_PULLUP, 0) /* (AA5) I2C0_SDA */
> + >;
> + };
> +
> + main_i2c1_pins_default: main-i2c1-pins-default {
> + pinctrl-single,pins = <
> + J721E_IOPAD(0x228, PIN_INPUT_PULLUP, 0) /* (Y6) I2C1_SCL */
> + J721E_IOPAD(0x22c, PIN_INPUT_PULLUP, 0) /* (AA6) I2C1_SDA */
> + >;
> + };
> +
> + main_i2c3_pins_default: main-i2c3-pins-default {
> + pinctrl-single,pins = <
> + J721E_IOPAD(0x270, PIN_INPUT_PULLUP, 4) /* (T26) MMC2_CLK.I2C3_SCL */
> + J721E_IOPAD(0x274, PIN_INPUT_PULLUP, 4) /* (T25) MMC2_CMD.I2C3_SDA */
> + >;
> + };
> +};
> +
> +&wkup_pmx0 {
> + mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-pins-default {
> + pinctrl-single,pins = <
> + J721E_WKUP_IOPAD(0x0, PIN_OUTPUT, 0) /* (E20) MCU_OSPI0_CLK */
> + J721E_WKUP_IOPAD(0x2c, PIN_OUTPUT, 0) /* (F19) MCU_OSPI0_CSn0 */
> + J721E_WKUP_IOPAD(0xc, PIN_INPUT, 0) /* (D20) MCU_OSPI0_D0 */
> + J721E_WKUP_IOPAD(0x10, PIN_INPUT, 0) /* (G19) MCU_OSPI0_D1 */
> + J721E_WKUP_IOPAD(0x14, PIN_INPUT, 0) /* (G20) MCU_OSPI0_D2 */
> + J721E_WKUP_IOPAD(0x18, PIN_INPUT, 0) /* (F20) MCU_OSPI0_D3 */
> + J721E_WKUP_IOPAD(0x1c, PIN_INPUT, 0) /* (F21) MCU_OSPI0_D4 */
> + J721E_WKUP_IOPAD(0x20, PIN_INPUT, 0) /* (E21) MCU_OSPI0_D5 */
> + J721E_WKUP_IOPAD(0x24, PIN_INPUT, 0) /* (B22) MCU_OSPI0_D6 */
> + J721E_WKUP_IOPAD(0x28, PIN_INPUT, 0) /* (G21) MCU_OSPI0_D7 */
> + J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */
> + >;
> + };
> +
> + vdd_mmc1_en_pins_default: vdd-mmc1-en-pins-default {
> + pinctrl-single,pins = <
> + J721E_WKUP_IOPAD(0xd0, PIN_OUTPUT, 7) /* (G27) WKUP_GPIO0_8 */
> + >;
> + };
> +
> + vdd_sd_dv_alt_pins_default: vdd-sd-dv-alt-pins-default {
> + pinctrl-single,pins = <
> + J721E_WKUP_IOPAD(0xd4, PIN_OUTPUT, 7) /* (G26) WKUP_GPIO0_9 */
> + >;
> + };
> +
> + wkup_i2c0_pins_default: wkup-i2c0-pins-default {
> + pinctrl-single,pins = <
> + J721E_WKUP_IOPAD(0xf8, PIN_INPUT_PULLUP, 0) /* (J25) WKUP_I2C0_SCL */
> + J721E_WKUP_IOPAD(0xfc, PIN_INPUT_PULLUP, 0) /* (H24) WKUP_I2C0_SDA */
> + >;
> + };
> +};
> +
> +&wkup_uart0 {
> + /* Wakeup UART is used by System firmware */
> + status = "reserved";
> +};
> +
> +&main_uart0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&main_uart0_pins_default>;
> + /* Shared with ATF on this platform */
> + power-domains = <&k3_pds 146 TI_SCI_PD_SHARED>;
> +};
> +
> +&main_uart2 {
> + /* Brought out on RPi header */
> + status = "disabled";
> +};
> +
> +&main_uart3 {
> + /* UART not brought out */
> + status = "disabled";
> +};
> +
> +&main_uart5 {
> + /* UART not brought out */
> + status = "disabled";
> +};
> +
> +&main_uart6 {
> + /* UART not brought out */
> + status = "disabled";
> +};
> +
> +&main_uart7 {
> + /* UART not brought out */
> + status = "disabled";
> +};
> +
> +&main_uart8 {
> + /* UART not brought out */
> + status = "disabled";
> +};
> +
> +&main_uart9 {
> + /* Brought out on M.2 E Key */
> + status = "disabled";
> +};
> +
> +&main_sdhci0 {
> + /* Unused */
> + status = "disabled";
> +};
> +
> +&main_sdhci1 {
> + /* SD Card */
> + vmmc-supply = <&vdd_mmc1>;
> + vqmmc-supply = <&vdd_sd_dv_alt>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&main_mmc1_pins_default>;
> + ti,driver-strength-ohm = <50>;
> + disable-wp;
> +};
> +
> +&main_sdhci2 {
> + /* Unused */
> + status = "disabled";
> +};
> +
> +&ospi0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&mcu_fss0_ospi0_pins_default>;
> +
> + flash@0{

flash@0<space>{

> + compatible = "jedec,spi-nor";
> + reg = <0x0>;
> + spi-tx-bus-width = <8>;
> + spi-rx-bus-width = <8>;
> + spi-max-frequency = <25000000>;
> + cdns,tshsl-ns = <60>;
> + cdns,tsd2d-ns = <60>;
> + cdns,tchsh-ns = <60>;
> + cdns,tslch-ns = <60>;
> + cdns,read-delay = <4>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + partition@3fc0000 {
> + label = "ospi.phypattern";
> + reg = <0x3fc0000 0x40000>;
> + u-boot,dm-spl;
> + };
> + };
> +};
> +
> +&ospi1 {
> + /* Unused */
> + status = "disabled";
> +};
> +
> +&main_i2c0 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&main_i2c0_pins_default>;
> + clock-frequency = <400000>;
> +
> + i2c-switch@71 {
> + compatible = "nxp,pca9543";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x71>;
> +
> + /* PCIe1 M.2 M Key I2C */
> + pcie1_m2_i2c: i2c@0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0>;
> + };
> +
> + /* PCIe0 M.2 E Key I2C */
> + pcie0_m2_i2c: i2c@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> + };
> + };
> +};
> +
> +&main_i2c1 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&main_i2c1_pins_default>;
> + clock-frequency = <400000>;
> +};
> +
> +&main_i2c3 {
> + pinctrl-names = "default";
> + pinctrl-0 = <&main_i2c3_pins_default>;
> + clock-frequency = <400000>;
> +
> + i2c-switch@70 {
> + compatible = "nxp,pca9543";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0x70>;
> +
> + /* CAM0 I2C */
> + ti_cam0_i2c: i2c@0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0>;
> + };
> +
> + /* CAM1 I2C */
> + rpi_cam0_i2c: i2c@1 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <1>;
> + };
> + };
> +};
> +
> +&main_i2c4 {
> + /* Unused */
> + status = "disabled";
> +};
> +
> +&main_i2c5 {
> + /* Brought out on RPi Header */
> + status = "disabled";
> +};
> +
> +&main_i2c6 {
> + /* Unused */
> + status = "disabled";
> +};

please also check other nodes that needs to be disabled or configured.

--
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3 1A34 DDB5 849D 1736 249D