Re: [PATCH 1/5] dt-bindings: dma: Document RZ/G2L bindings

[Rob Herring <robh@kernel.org>]

On Fri, Jun 11, 2021 at 12:36:38PM +0100, Biju Das wrote:
> Document RZ/G2L DMAC bindings.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
>  .../bindings/dma/renesas,rz-dmac.yaml         | 132 ++++++++++++++++++
>  1 file changed, 132 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> 
> diff --git a/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> new file mode 100644
> index 000000000000..df54bd6ddfd4
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/dma/renesas,rz-dmac.yaml
> @@ -0,0 +1,132 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/dma/renesas,rz-dmac.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Renesas RZ/G2L DMA Controller
> +
> +maintainers:
> +  - Biju Das <biju.das.jz@bp.renesas.com>
> +
> +allOf:
> +  - $ref: "dma-controller.yaml#"
> +
> +properties:
> +  compatible:
> +    items:
> +      - enum:
> +          - renesas,dmac-r9a07g044  # RZ/G2{L,LC}
> +      - const: renesas,rz-dmac
> +
> +  reg:
> +    items:
> +      - description: Control and channel register block
> +      - description: DMA extension resource selector block
> +
> +  interrupts:
> +    maxItems: 17
> +
> +  interrupt-names:
> +    maxItems: 17
> +    items:
> +      - pattern: "^ch([0-9]|1[0-5])$"
> +      - pattern: "^ch([0-9]|1[0-5])$"
> +      - pattern: "^ch([0-9]|1[0-5])$"
> +      - pattern: "^ch([0-9]|1[0-5])$"
> +      - pattern: "^ch([0-9]|1[0-5])$"
> +      - pattern: "^ch([0-9]|1[0-5])$"
> +      - pattern: "^ch([0-9]|1[0-5])$"
> +      - pattern: "^ch([0-9]|1[0-5])$"
> +      - pattern: "^ch([0-9]|1[0-5])$"
> +      - pattern: "^ch([0-9]|1[0-5])$"
> +      - pattern: "^ch([0-9]|1[0-5])$"
> +      - pattern: "^ch([0-9]|1[0-5])$"
> +      - pattern: "^ch([0-9]|1[0-5])$"
> +      - pattern: "^ch([0-9]|1[0-5])$"
> +      - pattern: "^ch([0-9]|1[0-5])$"
> +      - pattern: "^ch([0-9]|1[0-5])$"

Is there some reason these need be in undefined order?

> +      - const: error
> +
> +  clocks:
> +    maxItems: 1
> +
> +  '#dma-cells':
> +    const: 1
> +    description:
> +      The cell specifies the MID/RID of the DMAC port connected to
> +      the DMA client.
> +
> +  dma-channels:
> +    const: 16
> +
> +  power-domains:
> +    maxItems: 1
> +
> +  resets:
> +    maxItems: 1
> +
> +  renesas,rz-dmac-slavecfg:
> +    $ref: /schemas/types.yaml#/definitions/uint32-array
> +    description: |
> +      DMA configuration for a slave channel. Each channel must have an array of
> +      3 items as below.
> +      first item in the array is MID+RID
> +      second item in the array is slave src or dst address
> +      third item in the array is channel configuration value.

Why not put all these in the dma-cells? You already have 1 of them.

Though doesn't the client device know what address to use?

> +    items:
> +      minItems: 3
> +      maxItems: 48
> +
> +required:
> +  - compatible
> +  - reg
> +  - interrupts
> +  - interrupt-names
> +  - clocks
> +  - '#dma-cells'
> +  - dma-channels
> +  - power-domains
> +  - resets
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/interrupt-controller/arm-gic.h>
> +    #include <dt-bindings/clock/r9a07g044-cpg.h>
> +
> +    dmac: dma-controller@11820000 {
> +        compatible = "renesas,dmac-r9a07g044",
> +                     "renesas,rz-dmac";
> +        reg = <0x11820000 0x10000>,
> +              <0x11830000 0x10000>;
> +        interrupts = <GIC_SPI 125 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 126 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 127 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 128 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 130 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 131 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 133 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 135 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 137 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 139 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>,
> +                     <GIC_SPI 141 IRQ_TYPE_EDGE_RISING>;
> +        interrupt-names = "ch0", "ch1", "ch2", "ch3",
> +                          "ch4", "ch5", "ch6", "ch7",
> +                          "ch8", "ch9", "ch10", "ch11",
> +                          "ch12", "ch13", "ch14", "ch15",
> +                          "error";
> +        clocks = <&cpg CPG_MOD R9A07G044_CLK_DMAC>;
> +        power-domains = <&cpg>;
> +        resets = <&cpg R9A07G044_CLK_DMAC>;
> +        #dma-cells = <1>;
> +        dma-channels = <16>;
> +        renesas,rz-dmac-slavecfg = <0x255 0x10049C18 0x0011228>;
> +    };
> -- 
> 2.17.1