From: Tinghan Shen <tinghan.shen@mediatek.com>
To: <robh+dt@kernel.org>, <matthias.bgg@gmail.com>
Cc: <devicetree@vger.kernel.org>,
<linux-mediatek@lists.infradead.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <srv_heupstream@mediatek.com>,
<seiya.wang@mediatek.com>, <wenst@google.com>,
<Project_Global_Chrome_Upstream_Group@mediatek.com>,
Nancy Lin <nancy.lin@mediatek.com>
Subject: [PATCH 25/27] arm64: dts: mt8195: add vdosys1 support for MT8195
Date: Wed, 16 Jun 2021 01:32:31 +0800 [thread overview]
Message-ID: <20210615173233.26682-25-tinghan.shen@mediatek.com> (raw)
In-Reply-To: <20210615173233.26682-1-tinghan.shen@mediatek.com>
From: Nancy Lin <nancy.lin@mediatek.com>
add vdosys1 support for MT8195
Signed-off-by: Nancy Lin <nancy.lin@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 178 +++++++++++++++++++++--
1 file changed, 169 insertions(+), 9 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index e273833a49f8..a98609989905 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -26,6 +26,7 @@
dpi1 = &disp_dpi1;
dp-intf0 = &dp_intf0;
dp-intf1 = &dp_intf1;
+ merge5 = &merge5;
};
clocks {
@@ -2241,22 +2242,27 @@
vdosys_config@1c01a000 {
compatible = "mediatek,mt8195-vdosys";
- reg = <0 0x1c01a000 0 0x1000>;
- reg-names = "vdosys0_config";
+ reg = <0 0x1c01a000 0 0x1000>,<0 0x1c100000 0 0x1000>;
+ reg-names = "vdosys0_config","vdosys1_config";
iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
- mboxes = <&gce1 0 0 CMDQ_THR_PRIO_4>;
+ mboxes = <&gce1 0 0 CMDQ_THR_PRIO_4>,
+ <&gce1 1 0 CMDQ_THR_PRIO_4>;
};
mutex: disp_mutex0@1c016000 {
compatible = "mediatek,mt8195-disp-mutex";
- reg = <0 0x1c016000 0 0x1000>;
- reg-names = "vdo0_mutex";
- clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
+ reg = <0 0x1c016000 0 0x1000>,
+ <0 0x1c101000 0 0x1000>;
+ reg-names = "vdo0_mutex","vdo1_mutex";
+ clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>,
+ <&vdosys1 CLK_VDO1_DISP_MUTEX>;
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
- clock-names = "vdo0_mutex";
- interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
- mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
+ clock-names = "vdo0_mutex","sub_mutex";
+ interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH 0>;
+ mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>,
+ <CMDQ_EVENT_VDO1_STREAM_DONE_ENG_0>;
};
ovl0: disp_ovl@1c000000 {
@@ -2446,6 +2452,92 @@
power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
};
+ disp_pseudo_ovl0@1c104000 {
+ compatible = "mediatek,mt8195-disp-pseudo-ovl";
+ reg = <0 0x1c104000 0 0x1000>,
+ <0 0x1c105000 0 0x1000>,
+ <0 0x1c106000 0 0x1000>,
+ <0 0x1c107000 0 0x1000>,
+ <0 0x1c108000 0 0x1000>,
+ <0 0x1c109000 0 0x1000>,
+ <0 0x1c10A000 0 0x1000>,
+ <0 0x1c10B000 0 0x1000>,
+ <0 0x1c10C000 0 0x1000>,
+ <0 0x1c10D000 0 0x1000>,
+ <0 0x1c10E000 0 0x1000>,
+ <0 0x1c10F000 0 0x1000>,
+ <0 0x1c100000 0 0x1000>;
+ reg-names = "vdo1_mdp_rdma0","vdo1_mdp_rdma1","vdo1_mdp_rdma2",
+ "vdo1_mdp_rdma3","vdo1_mdp_rdma4",
+ "vdo1_mdp_rdma5","vdo1_mdp_rdma6",
+ "vdo1_mdp_rdma7","vdo1_merge0",
+ "vdo1_merge1","vdo1_merge2","vdo1_merge3","top";
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c10XXXX 0x4000 0x1000>,
+ <&gce1 SUBSYS_1c10XXXX 0x5000 0x1000>,
+ <&gce1 SUBSYS_1c10XXXX 0x6000 0x1000>,
+ <&gce1 SUBSYS_1c10XXXX 0x7000 0x1000>,
+ <&gce1 SUBSYS_1c10XXXX 0x8000 0x1000>,
+ <&gce1 SUBSYS_1c10XXXX 0x9000 0x1000>,
+ <&gce1 SUBSYS_1c10XXXX 0xA000 0x1000>,
+ <&gce1 SUBSYS_1c10XXXX 0xB000 0x1000>,
+ <&gce1 SUBSYS_1c10XXXX 0xC000 0x1000>,
+ <&gce1 SUBSYS_1c10XXXX 0xD000 0x1000>,
+ <&gce1 SUBSYS_1c10XXXX 0xE000 0x1000>,
+ <&gce1 SUBSYS_1c10XXXX 0xF000 0x1000>,
+ <&gce1 SUBSYS_1c10XXXX 0x0000 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_MDP_RDMA0>,
+ <&vdosys1 CLK_VDO1_MDP_RDMA1>,
+ <&vdosys1 CLK_VDO1_MDP_RDMA2>,
+ <&vdosys1 CLK_VDO1_MDP_RDMA3>,
+ <&vdosys1 CLK_VDO1_MDP_RDMA4>,
+ <&vdosys1 CLK_VDO1_MDP_RDMA5>,
+ <&vdosys1 CLK_VDO1_MDP_RDMA6>,
+ <&vdosys1 CLK_VDO1_MDP_RDMA7>,
+ <&vdosys1 CLK_VDO1_VPP_MERGE0>,
+ <&vdosys1 CLK_VDO1_VPP_MERGE1>,
+ <&vdosys1 CLK_VDO1_VPP_MERGE2>,
+ <&vdosys1 CLK_VDO1_VPP_MERGE3>,
+ <&vdosys1 CLK_VDO1_MERGE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_MERGE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_MERGE2_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_MERGE3_DL_ASYNC>;
+ clock-names = "vdo1_mdp_rdma0","vdo1_mdp_rdma1",
+ "vdo1_mdp_rdma2","vdo1_mdp_rdma3",
+ "vdo1_mdp_rdma4","vdo1_mdp_rdma5",
+ "vdo1_mdp_rdma6","vdo1_mdp_rdma7",
+ "vdo1_merge0","vdo1_merge1",
+ "vdo1_merge2","vdo1_merge3",
+ "vdo1_merge0_async","vdo1_merge1_async",
+ "vdo1_merge2_async","vdo1_merge3_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,larb = <&larb2>;
+ mediatek,smi-id = <0>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>;
+ interrupts = <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH 0>, /*rdma0*/
+ <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH 0>, /*rdma1*/
+ <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH 0>, /*rdma2*/
+ <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH 0>, /*rdma3*/
+ <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH 0>, /*rdma4*/
+ <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH 0>, /*rdma5*/
+ <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH 0>, /*rdma6*/
+ <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH 0>, /*rdma7*/
+ <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH 0>, /*merge0*/
+ <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH 0>, /*merge1*/
+ <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH 0>, /*merge2*/
+ <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH 0>; /*merge3*/
+ };
+
+ merge5: disp_vpp_merge5@1c110000 {
+ compatible = "mediatek,mt8195-disp-merge";
+ reg = <0 0x1c110000 0 0x1000>;
+ interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vdosys1 CLK_VDO1_VPP_MERGE4>,
+ <&vdosys1 CLK_VDO1_MERGE4_DL_ASYNC>;
+ clock-names = "merge5","merge5_async";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x0000 0x1000>;
+ };
+
disp_dpi1: disp_dpi1@1c112000 {
compatible = "mediatek,mt8195-dpi";
reg = <0 0x1c112000 0 0x1000>;
@@ -2478,6 +2570,54 @@
status = "disabled";
};
+ disp_ethdr@1c114000 {
+ compatible = "mediatek,mt8195-disp-ethdr";
+ reg = <0 0x1c114000 0 0x1000>,
+ <0 0x1c115000 0 0x1000>,
+ <0 0x1c117000 0 0x1000>,
+ <0 0x1c119000 0 0x1000>,
+ <0 0x1c11A000 0 0x1000>,
+ <0 0x1c11B000 0 0x1000>,
+ <0 0x1c11C000 0 0x1000>,
+ <0 0x1c100000 0 0x1000>;
+ reg-names = "hdr_disp_mixer","hdr_vdo_fe0","hdr_vdo_fe1",
+ "hdr_gfx_fe0","hdr_gfx_fe1","hdr_vdo_be",
+ "hdr_adl_ds","top";
+ mediatek,gce-client-reg = <&gce1 SUBSYS_1c11XXXX 0x4000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x5000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x7000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0x9000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xA000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xB000 0x1000>,
+ <&gce1 SUBSYS_1c11XXXX 0xC000 0x1000>,
+ <&gce1 SUBSYS_1c10XXXX 0x0000 0x1000>;
+ clocks = <&vdosys1 CLK_VDO1_DISP_MIXER>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE>,
+ <&vdosys1 CLK_VDO1_26M_SLOW>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE0_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_GFX_FE1_DL_ASYNC>,
+ <&vdosys1 CLK_VDO1_HDR_VDO_BE_DL_ASYNC>,
+ <&topckgen CLK_TOP_ETHDR_SEL>;
+ clock-names = "hdr_disp_mixer","hdr_vdo_fe0","hdr_vdo_fe1",
+ "hdr_gfx_fe0","hdr_gfx_fe1","hdr_vdo_be",
+ "hdr_adl_ds","hdr_vdo_fe0_async",
+ "hdr_vdo_fe1_async","hdr_gfx_fe0_async",
+ "hdr_gfx_fe1_async","hdr_vdo_be_async",
+ "ethdr_top";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ mediatek,larb = <&larb3>;
+ mediatek,smi-id = <1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_HDR_DS>,
+ <&iommu_vpp M4U_PORT_L3_HDR_ADL>;
+ interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>; /*disp mixer*/
+ };
+
hdmi0: hdmi@1c300000 {
compatible = "mediatek,mt8195-hdmi";
reg = <0 0x1c300000 0 0x1000>;
@@ -2517,6 +2657,26 @@
};
};
+ disp_pseudo_ovl_l2 {
+ compatible = "mediatek,mt8195-pseudo-ovl-larb";
+ mediatek,larb-id = <2>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vdo M4U_PORT_L2_MDP_RDMA0>,
+ <&iommu_vdo M4U_PORT_L2_MDP_RDMA2>,
+ <&iommu_vdo M4U_PORT_L2_MDP_RDMA4>,
+ <&iommu_vdo M4U_PORT_L2_MDP_RDMA6>;
+ };
+
+ disp_pseudo_ovl_l3 {
+ compatible = "mediatek,mt8195-pseudo-ovl-larb";
+ mediatek,larb-id = <3>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ iommus = <&iommu_vpp M4U_PORT_L3_MDP_RDMA1>,
+ <&iommu_vpp M4U_PORT_L3_MDP_RDMA3>,
+ <&iommu_vpp M4U_PORT_L3_MDP_RDMA5>,
+ <&iommu_vpp M4U_PORT_L3_MDP_RDMA7>;
+ };
+
hdmiddc0: ddc_i2c {
compatible = "mediatek,mt8195-hdmi-ddc";
clocks = <&clk26m>;
--
2.18.0
next prev parent reply other threads:[~2021-06-15 17:33 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-15 17:32 arm64: dts: mt8195: Add Mediatek SoC MT8195 device nodes Tinghan Shen
2021-06-15 17:32 ` [PATCH 01/27] arm64: dts: mt8195: add infracfg_rst node Tinghan Shen
2021-06-16 8:01 ` Chen-Yu Tsai
2021-06-15 17:32 ` [PATCH 02/27] arm64: dts: mt8195: add pinctrl node Tinghan Shen
2021-06-15 17:32 ` [PATCH 03/27] arm64: dts: mt8195: add pwrap node Tinghan Shen
2021-06-15 17:32 ` [PATCH 05/27] arm64: dts: mt8195: add spmi node Tinghan Shen
2021-06-15 17:32 ` [PATCH 06/27] arm64: dts: mt8195: add clock controllers Tinghan Shen
2021-06-15 17:32 ` [PATCH 07/27] arm64: dts: mt8195: add power domains controller Tinghan Shen
2021-06-15 17:32 ` [PATCH 08/27] arm64: dts: mt8195: add i2c dts Tinghan Shen
2021-06-15 17:32 ` [PATCH 09/27] arm64: dts: mt8195: add spi controller Tinghan Shen
2021-06-15 17:32 ` [PATCH 10/27] arm64: dts: mt8195: add PCIe phy device node Tinghan Shen
2021-06-15 17:32 ` [PATCH 11/27] arm64: dts: mt8195: add PCIe " Tinghan Shen
2021-06-15 17:32 ` [PATCH 12/27] arm64: dts: mt8195: fix mmc driver Tinghan Shen
2021-06-16 1:30 ` Wenbin Mei
2021-06-15 17:32 ` [PATCH 13/27] arm64: dts: mt8195: add hdmi nodes Tinghan Shen
2021-06-15 17:32 ` [PATCH 14/27] arm64: dts: mt8195: add usb support Tinghan Shen
2021-06-15 17:32 ` [PATCH 15/27] arm64: dts: mt8195: add IOMMU and smi nodes Tinghan Shen
2021-06-15 17:32 ` [PATCH 16/27] arm64: dts: mt8195: add display node Tinghan Shen
2021-06-15 23:14 ` Chun-Kuang Hu
2021-06-15 17:32 ` [PATCH 17/27] arm64: dts: mt8195: add merge node Tinghan Shen
2021-06-15 17:32 ` [PATCH 18/27] arm64: dts: mt8195: add dsc node Tinghan Shen
2021-06-15 17:32 ` [PATCH 19/27] arm64: dts: mt8195: add dp_intf node Tinghan Shen
2021-06-15 17:32 ` [PATCH 20/27] arm64: dts: mt8195: fix nor_flash node Tinghan Shen
2021-06-15 17:32 ` [PATCH 21/27] arm64: dts: mt8195: add audio related nodes Tinghan Shen
2021-06-15 17:32 ` [PATCH 22/27] arm64: dts: mt8195: add edp nodes Tinghan Shen
2021-06-15 23:30 ` Chun-Kuang Hu
2021-06-15 17:32 ` [PATCH 23/27] arm64: dts: mt8195: add gce node Tinghan Shen
2021-06-18 14:07 ` Chun-Kuang Hu
2021-06-15 17:32 ` [PATCH 24/27] arm64: dts: mt8195: add gce setting for disply node Tinghan Shen
2021-06-15 17:32 ` Tinghan Shen [this message]
2021-06-15 23:23 ` [PATCH 25/27] arm64: dts: mt8195: add vdosys1 support for MT8195 Chun-Kuang Hu
2021-06-15 17:32 ` [PATCH 26/27] arm64: dts: mt8195: add scp device node Tinghan Shen
2021-06-15 17:32 ` [PATCH 27/27] arm64: dts: mt8195: add cpufreq device nodes Tinghan Shen
2021-06-18 14:21 ` arm64: dts: mt8195: Add Mediatek SoC MT8195 " Matthias Brugger
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