* [PATCH AUTOSEL 5.12 39/39] riscv: dts: fu740: fix cache-controller interrupts
[not found] <20210621175156.735062-1-sashal@kernel.org>
@ 2021-06-21 17:51 ` Sasha Levin
0 siblings, 0 replies; only message in thread
From: Sasha Levin @ 2021-06-21 17:51 UTC (permalink / raw)
To: linux-kernel, stable
Cc: David Abdurachmanov, Palmer Dabbelt, Sasha Levin, devicetree,
linux-riscv
From: David Abdurachmanov <david.abdurachmanov@sifive.com>
[ Upstream commit 7ede12b01b59dc67bef2e2035297dd2da5bfe427 ]
The order of interrupt numbers is incorrect.
The order for FU740 is: DirError, DataError, DataFail, DirFail
From SiFive FU740-C000 Manual:
19 - L2 Cache DirError
20 - L2 Cache DirFail
21 - L2 Cache DataError
22 - L2 Cache DataFail
Signed-off-by: David Abdurachmanov <david.abdurachmanov@sifive.com>
Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
index eeb4f8c3e0e7..d0d206cdb999 100644
--- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
@@ -272,7 +272,7 @@ ccache: cache-controller@2010000 {
cache-size = <2097152>;
cache-unified;
interrupt-parent = <&plic0>;
- interrupts = <19 20 21 22>;
+ interrupts = <19 21 22 20>;
reg = <0x0 0x2010000 0x0 0x1000>;
};
gpio: gpio@10060000 {
--
2.30.2
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2021-06-21 17:51 ` [PATCH AUTOSEL 5.12 39/39] riscv: dts: fu740: fix cache-controller interrupts Sasha Levin
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