From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.1 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS, URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 93A8FC11F6A for ; Fri, 2 Jul 2021 10:23:19 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 6F9AB61421 for ; Fri, 2 Jul 2021 10:23:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231451AbhGBKZu (ORCPT ); Fri, 2 Jul 2021 06:25:50 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43194 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231474AbhGBKZt (ORCPT ); Fri, 2 Jul 2021 06:25:49 -0400 Received: from mail-pf1-x430.google.com (mail-pf1-x430.google.com [IPv6:2607:f8b0:4864:20::430]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 2254DC061762 for ; Fri, 2 Jul 2021 03:23:17 -0700 (PDT) Received: by mail-pf1-x430.google.com with SMTP id g21so8525005pfc.11 for ; Fri, 02 Jul 2021 03:23:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=UQMYs79zEZ9cRPxEWnt8NOjSh4NRvCnWnv+pz9y9wNY=; b=PwctM/niWuHFFDZngtCSzCOdsXOOeeTV0vHuTTdDqdnskpgMYuxNX4XNP6n6BZ7N0p 4V+LFpPgR91uvjNy8W9xpKOu38FlwITSFRjvGMKI+tXd3+yNn9X6PkDEl3dv9fqXNkI4 mxoHwFyTTX+LiwfG/ozYa/fhPWNewIIgf4tfU= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=UQMYs79zEZ9cRPxEWnt8NOjSh4NRvCnWnv+pz9y9wNY=; b=Iqc5YrN+QlzQt637nYU2JmziGxSv0fAskHWKTJsDJOCVZ8bLXBtqa4LK7YjnafcQ9G hbF15IaawkMsOH8FeAiRruhbPI8KjZnsHBkPNEQCAsELxOvfyvXpFy70wmP2JmedgTbZ vSBLWhfzz28duW2Q9ZepOpgQ2lgs4FnUhVPNL1seJA8OyvUPQobFWuZUELrt41Ry0ibd Lkt7m0EDHBtUwfB/podxe20tE/OwRtqP8j2hRZIRPZwsPJNG5DB+JlXuvxqkxScv7tTu GsyGXeq94/qFkbLtj905YUk7dqwBqfPT12G0EVUv5aMWd3uuewo0YnKgb7gyjFJh8D05 cI3A== X-Gm-Message-State: AOAM531fze9u8xStdPwg1+MxmMKqAVQ3etGbnNEPHvkyhLR7xgDt7DmM AjKXLVn9gTa62tKs2tLfXGmrBg== X-Google-Smtp-Source: ABdhPJxXn/xM65ulk5EJtA5BL3WqwTO2Rmq/NSmSZHW63r1jiZiQitM6a1gZq/I/pQVM3jXtKYNt2A== X-Received: by 2002:a63:4e4d:: with SMTP id o13mr971062pgl.361.1625221396404; Fri, 02 Jul 2021 03:23:16 -0700 (PDT) Received: from hsinyi-z840.tpe.corp.google.com ([2401:fa00:1:10:b63b:3ac0:4dda:fdd2]) by smtp.gmail.com with ESMTPSA id d13sm2863484pfn.136.2021.07.02.03.23.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 02 Jul 2021 03:23:15 -0700 (PDT) From: Hsin-Yi Wang To: Matthias Brugger , Rob Herring , Mauro Carvalho Chehab Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-kernel@vger.kernel.org, maoguang.meng@mediatek.com, yong.wu@mediatek.com Subject: [PATCH v5 RESEND 1/3] dt-bindings: mediatek: convert mtk jpeg decoder/encoder to yaml Date: Fri, 2 Jul 2021 18:23:02 +0800 Message-Id: <20210702102304.3346429-1-hsinyi@chromium.org> X-Mailer: git-send-email 2.32.0.93.g670b81a890-goog MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Convert mediatek jpeg decoder and encoder bindings to yaml. Signed-off-by: Hsin-Yi Wang Reviewed-by: Rob Herring --- .../bindings/media/mediatek-jpeg-decoder.txt | 38 -------- .../bindings/media/mediatek-jpeg-decoder.yaml | 89 +++++++++++++++++++ .../bindings/media/mediatek-jpeg-encoder.txt | 35 -------- .../bindings/media/mediatek-jpeg-encoder.yaml | 80 +++++++++++++++++ 4 files changed, 169 insertions(+), 73 deletions(-) delete mode 100644 Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.txt create mode 100644 Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.yaml delete mode 100644 Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.txt create mode 100644 Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml diff --git a/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.txt b/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.txt deleted file mode 100644 index 39c1028b2dfb4..0000000000000 --- a/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.txt +++ /dev/null @@ -1,38 +0,0 @@ -* Mediatek JPEG Decoder - -Mediatek JPEG Decoder is the JPEG decode hardware present in Mediatek SoCs - -Required properties: -- compatible : must be one of the following string: - "mediatek,mt8173-jpgdec" - "mediatek,mt7623-jpgdec", "mediatek,mt2701-jpgdec" - "mediatek,mt2701-jpgdec" -- reg : physical base address of the jpeg decoder registers and length of - memory mapped region. -- interrupts : interrupt number to the interrupt controller. -- clocks: device clocks, see - Documentation/devicetree/bindings/clock/clock-bindings.txt for details. -- clock-names: must contain "jpgdec-smi" and "jpgdec". -- power-domains: a phandle to the power domain, see - Documentation/devicetree/bindings/power/power_domain.txt for details. -- mediatek,larb: must contain the local arbiters in the current Socs, see - Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml - for details. -- iommus: should point to the respective IOMMU block with master port as - argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml - for details. - -Example: - jpegdec: jpegdec@15004000 { - compatible = "mediatek,mt2701-jpgdec"; - reg = <0 0x15004000 0 0x1000>; - interrupts = ; - clocks = <&imgsys CLK_IMG_JPGDEC_SMI>, - <&imgsys CLK_IMG_JPGDEC>; - clock-names = "jpgdec-smi", - "jpgdec"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; - mediatek,larb = <&larb2>; - iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>, - <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>; - }; diff --git a/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.yaml b/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.yaml new file mode 100644 index 0000000000000..9b87f036f1785 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek-jpeg-decoder.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek-jpeg-decoder.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek JPEG Decoder Device Tree Bindings + +maintainers: + - Xia Jiang + +description: |- + Mediatek JPEG Decoder is the JPEG decode hardware present in Mediatek SoCs + +properties: + compatible: + oneOf: + - items: + - enum: + - mediatek,mt8173-jpgdec + - mediatek,mt2701-jpgdec + - items: + - enum: + - mediatek,mt7623-jpgdec + - const: mediatek,mt2701-jpgdec + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 2 + minItems: 2 + + clock-names: + items: + - const: jpgdec-smi + - const: jpgdec + + power-domains: + maxItems: 1 + + mediatek,larb: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: | + Must contain the local arbiters in the current Socs, see + Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml + for details. + + iommus: + maxItems: 2 + description: | + Points to the respective IOMMU block with master port as argument, see + Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. + Ports are according to the HW. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - power-domains + - mediatek,larb + - iommus + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + jpegdec: jpegdec@15004000 { + compatible = "mediatek,mt2701-jpgdec"; + reg = <0x15004000 0x1000>; + interrupts = ; + clocks = <&imgsys CLK_IMG_JPGDEC_SMI>, + <&imgsys CLK_IMG_JPGDEC>; + clock-names = "jpgdec-smi", + "jpgdec"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; + mediatek,larb = <&larb2>; + iommus = <&iommu MT2701_M4U_PORT_JPGDEC_WDMA>, + <&iommu MT2701_M4U_PORT_JPGDEC_BSDMA>; + }; diff --git a/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.txt b/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.txt deleted file mode 100644 index 5e53c6ab52d01..0000000000000 --- a/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.txt +++ /dev/null @@ -1,35 +0,0 @@ -* MediaTek JPEG Encoder - -MediaTek JPEG Encoder is the JPEG encode hardware present in MediaTek SoCs - -Required properties: -- compatible : "mediatek,mt2701-jpgenc" - followed by "mediatek,mtk-jpgenc" -- reg : physical base address of the JPEG encoder registers and length of - memory mapped region. -- interrupts : interrupt number to the interrupt controller. -- clocks: device clocks, see - Documentation/devicetree/bindings/clock/clock-bindings.txt for details. -- clock-names: must contain "jpgenc". It is the clock of JPEG encoder. -- power-domains: a phandle to the power domain, see - Documentation/devicetree/bindings/power/power_domain.txt for details. -- mediatek,larb: must contain the local arbiters in the current SoCs, see - Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml - for details. -- iommus: should point to the respective IOMMU block with master port as - argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml - for details. - -Example: - jpegenc: jpegenc@1500a000 { - compatible = "mediatek,mt2701-jpgenc", - "mediatek,mtk-jpgenc"; - reg = <0 0x1500a000 0 0x1000>; - interrupts = ; - clocks = <&imgsys CLK_IMG_VENC>; - clock-names = "jpgenc"; - power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; - mediatek,larb = <&larb2>; - iommus = <&iommu MT2701_M4U_PORT_JPGENC_RDMA>, - <&iommu MT2701_M4U_PORT_JPGENC_BSDMA>; - }; diff --git a/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml b/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml new file mode 100644 index 0000000000000..5e35ecfd21f1b --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.yaml @@ -0,0 +1,80 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek-jpeg-encoder.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek JPEG Encoder Device Tree Bindings + +maintainers: + - Xia Jiang + +description: |- + MediaTek JPEG Encoder is the JPEG encode hardware present in MediaTek SoCs + +properties: + compatible: + items: + - enum: + - mediatek,mt2701-jpgenc + - const: mediatek,mtk-jpgenc + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: jpgenc + + power-domains: + maxItems: 1 + + mediatek,larb: + $ref: '/schemas/types.yaml#/definitions/phandle' + description: | + Must contain the local arbiters in the current Socs, see + Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.yaml + for details. + + iommus: + maxItems: 2 + description: | + Points to the respective IOMMU block with master port as argument, see + Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml for details. + Ports are according to the HW. + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - power-domains + - mediatek,larb + - iommus + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + jpegenc: jpegenc@1500a000 { + compatible = "mediatek,mt2701-jpgenc", + "mediatek,mtk-jpgenc"; + reg = <0x1500a000 0x1000>; + interrupts = ; + clocks = <&imgsys CLK_IMG_VENC>; + clock-names = "jpgenc"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; + mediatek,larb = <&larb2>; + iommus = <&iommu MT2701_M4U_PORT_JPGENC_RDMA>, + <&iommu MT2701_M4U_PORT_JPGENC_BSDMA>; + }; -- 2.32.0.93.g670b81a890-goog