[Patch v3 6/6] dt-bindings: thermal: Add dt binding for QCOM LMh

Thara Gopinath
2021-07-08T12:07:11Z

Add dt binding documentation to describe Qualcomm
Limits Management Hardware node.

Signed-off-by: Thara Gopinath <thara.gopinath@linaro.org>
---
.../devicetree/bindings/thermal/qcom-lmh.yaml | 100 ++++++++++++++++++
1 file changed, 100 insertions(+)
create mode 100644 Documentation/devicetree/bindings/thermal/qcom-lmh.yaml

diff --git a/Documentation/devicetree/bindings/thermal/qcom-lmh.yaml b/Documentation/devicetree/bindings/thermal/qcom-lmh.yaml
new file mode 100644
index 000000000000..7f62bd3d543d
--- /dev/null
+++ b/Documentation/devicetree/bindings/thermal/qcom-lmh.yaml
@@ -0,0 +1,100 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright 2021 Linaro Ltd.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/thermal/qcom-lmh.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Limits Management Hardware(LMh)
+
+maintainers:
+ - Thara Gopinath <thara.gopinath@linaro.org>
+
+description:
+ Limits Management Hardware(LMh) is a hardware infrastructure on some
+ Qualcomm SoCs that can enforce temperature and current limits as
+ programmed by software for certain IPs like CPU.
+
+properties:
+ compatible:
+ enum:
+ - qcom,sdm845-lmh
+
+ reg:
+ items:
+ - description: core registers
+
+ interrupts:
+ maxItems: 1
+
+ '#interrupt-cells':
+ const: 1
+
+ interrupt-controller: true
+
+ qcom,lmh-cpu-id:
+ description:
+ CPU id of the first cpu in the LMh cluster
+ $ref: /schemas/types.yaml#/definitions/uint32
+
+ qcom,lmh-temperature-arm:
+ description:
+ An integer expressing temperature threshold in millicelsius at which
+ the LMh thermal FSM is engaged.
+ $ref: /schemas/types.yaml#/definitions/int32
+
+ qcom,lmh-temperature-low:
+ description:
+ An integer expressing temperature threshold in millicelsius at which
+ the LMh thermal FSM is engaged.
+ $ref: /schemas/types.yaml#/definitions/int32
+
+ qcom,lmh-temperature-high:
+ description:
+ An integer expressing temperature threshold in millicelsius at which
+ the LMh thermal FSM is engaged.
+ $ref: /schemas/types.yaml#/definitions/int32
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - #interrupt-cells
+ - interrupt-controller
+ - qcom,lmh-cpu-id
+ - qcom,lmh-temperature-arm
+ - qcom,lmh-temperature-low
+ - qcom,lmh-temperature-high
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/qcom,rpmh.h>
+ #include <dt-bindings/interconnect/qcom,sdm845.h>
+
+ lmh_cluster1: lmh@17d70800 {
+ compatible = "qcom,sdm845-lmh";
+ reg = <0 0x17d70800 0 0x401>;
+ interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,lmh-cpu-id = <0x4>;
+ qcom,lmh-temperature-arm = <65000>;
+ qcom,lmh-temperature-low = <94500>;
+ qcom,lmh-temperature-high = <95000>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ - |
+ lmh_cluster0: lmh@17d78800 {
+ compatible = "qcom,sdm845-lmh";
+ reg = <0 0x17d78800 0 0x401>;
+ interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
+ qcom,lmh-cpu-id = <0x0>;
+ qcom,lmh-temperature-arm = <65000>;
+ qcom,lmh-temperature-low = <94500>;
+ qcom,lmh-temperature-high = <95000>;
+ interrupt-controller;
+ #interrupt-cells = <1>;
+ };
+ - |
--
2.25.1