From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.3 required=3.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,DKIM_VALID_AU,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D68CBC11F68 for ; Mon, 12 Jul 2021 08:09:05 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C80466194F for ; Mon, 12 Jul 2021 08:09:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S245344AbhGLILt (ORCPT ); Mon, 12 Jul 2021 04:11:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:48232 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1353276AbhGLIBs (ORCPT ); Mon, 12 Jul 2021 04:01:48 -0400 Received: from mail-pf1-x42f.google.com (mail-pf1-x42f.google.com [IPv6:2607:f8b0:4864:20::42f]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F0214C0610EF for ; Mon, 12 Jul 2021 00:53:07 -0700 (PDT) Received: by mail-pf1-x42f.google.com with SMTP id q10so15596566pfj.12 for ; Mon, 12 Jul 2021 00:53:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to:user-agent; bh=8H0yUJOEvi3zZTuxDoA57QDVjTfFiJnGcoqqzbwxmVs=; b=ZG5p7Tqp7gaCXtfqcGueAgC03BaZ6tkCjgmLL+HntOiwhJVqLV6P6FH1PU6ijigIwa 2D4aHrU2WxmK0t/cVP5bhnfA6Hkfog08BhnyIsOcgCOM9FnYRcvnd7v6hZUq3SbkC8p8 drICwrUijHqS3WKlo2GtM6VUvreUSiSm45XYaSrDodqEoAdcJwkF91hPc2NmPEe2cBy8 Ln6qOoZO1+4J3z+jn4vMSOYSxCAI7XrZrZj0PRJtLPs4Ww9EUDq+huGj459Y7BO1sr9d e2PNoPqExJBslLp/TZZ8xwXSDQ/72n1gP1FAu2OXrZICejo4aQ5No5TQFgZsULmFensl vafw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to:user-agent; bh=8H0yUJOEvi3zZTuxDoA57QDVjTfFiJnGcoqqzbwxmVs=; b=Qz82Jj9cFjxDslyFgyJnvRvfwyqezJiukk48d3PavCLrOqD2f7b9xW7HYJmbH/6edU qCqaP43wuno0Yr/xSzkbZ3nGj5Ft2ZXih8Tg1mDuveqyejKd2r3bFWuniGZ2W1GBYPTV UTr9NfZuza9UIGxhaQql//q/3YViP8RLjgxPp6qXu8q2AfI0D6u72kQJC3eQKqUjwuYB l+/BBZXjQRHMBqCFk8KVfogyWJ/0fOBvpuTOm64leQr+usDsTFlHlH25neO7HbNohYWg Lne4vJQMX2V424n0eHatPmxl8//nOaYb6RMY3qNqP1z2e/x1oUZf02uEK0TyBsbpLMXd NtxA== X-Gm-Message-State: AOAM531t4cxMUgTSoxeOhBGNmH2E+JjTfptqYB/7LpFJKpfR1a/04e8x CUqnzzzLqk74ZT6ZofeQwg0t X-Google-Smtp-Source: ABdhPJwSTnl9VFCmFcSRDus9OJnYbw708x25bRrEGojoECLrgUODo4vjpCMqB2mk+hCd78dAXbA+kw== X-Received: by 2002:a62:1d86:0:b029:32a:311a:9595 with SMTP id d128-20020a621d860000b029032a311a9595mr10855485pfd.74.1626076387347; Mon, 12 Jul 2021 00:53:07 -0700 (PDT) Received: from workstation ([120.138.12.18]) by smtp.gmail.com with ESMTPSA id z3sm16409753pgl.77.2021.07.12.00.53.03 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 12 Jul 2021 00:53:07 -0700 (PDT) Date: Mon, 12 Jul 2021 13:23:02 +0530 From: Manivannan Sadhasivam To: Rob Herring Cc: Kishon Vijay Abraham I , Lorenzo Pieralisi , Bjorn Helgaas , devicetree@vger.kernel.org, PCI , "linux-kernel@vger.kernel.org" , linux-arm-msm , hemantk@codeaurora.org, Siddartha Mohanadoss , Bjorn Andersson , Sriharsha Allenki , skananth@codeaurora.org, vpernami@codeaurora.org, Veerabhadrarao Badiganti Subject: Re: [PATCH v5 0/3] Add Qualcomm PCIe Endpoint driver support Message-ID: <20210712075302.GA8113@workstation> References: <20210630034653.10260-1-manivannan.sadhasivam@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.9.4 (2018-02-28) Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Thu, Jul 01, 2021 at 09:25:01AM -0600, Rob Herring wrote: > On Tue, Jun 29, 2021 at 9:47 PM Manivannan Sadhasivam > wrote: > > > > Hello, > > > > This series adds support for Qualcomm PCIe Endpoint controller found > > in platforms like SDX55. The Endpoint controller is based on the designware > > core with additional Qualcomm wrappers around the core. > > > > The driver is added separately unlike other Designware based drivers that > > combine RC and EP in a single driver. This is done to avoid complexity and > > to maintain this driver autonomously. > > > > The driver has been validated with an out of tree MHI function driver on > > SDX55 based Telit FN980 EVB connected to x86 host machine over PCIe. > > > > Thanks, > > Mani > > > > Changes in v5: > > > > * Removed the DBI register settings that are not needed > > * Used the standard definitions available in pci_regs.h > > * Added defines for all the register fields > > * Removed the left over code from previous iteration > > > > Changes in v4: > > > > * Removed the active_config settings needed for IPA integration > > * Switched to writel for couple of relaxed versions that sneaked in > > I thought we resolved this discussion. Use _relaxed variants unless > you need the stronger ones. > I thought the discussion was resolved in favor of using read/writel. Here is the last reply from Bjorn: "I think we came to the conclusion that writel() was better than incorrect use of writel_relaxed() followed by wmb(). And in this particular case it's definitely not happening in a hot code path..." IMO, it is safer to use readl/writel calls than the relaxed variants. And so far the un-written rule I assumed is, only consider using the relaxed variants if the code is in hot path (but somehow I used the relaxed version in v1 :P ) Thanks, Mani > Rob > > > > > Changes in v3: > > > > * Lot of minor cleanups to the driver patch based on review from Bjorn and Stan. > > * Noticeable changes are: > > - Got rid of _relaxed calls and used readl/writel > > - Got rid of separate TCSR memory region and used syscon for getting the > > register offsets for Perst registers > > - Changed the wake gpio handling logic > > - Added remove() callback and removed "suppress_bind_attrs" > > - stop_link() callback now just disables PERST IRQ > > * Added MMIO region and doorbell interrupt to the binding > > * Added logic to write MMIO physicall address to MHI base address as it is > > for the function driver to work > > > > Changes in v2: > > > > * Addressed the comments from Rob on bindings patch > > * Modified the driver as per binding change > > * Fixed the warnings reported by Kbuild bot > > * Removed the PERST# "enable_irq" call from probe() > > > > Manivannan Sadhasivam (3): > > dt-bindings: pci: Add devicetree binding for Qualcomm PCIe EP > > controller > > PCI: dwc: Add Qualcomm PCIe Endpoint controller driver > > MAINTAINERS: Add entry for Qualcomm PCIe Endpoint driver and binding > > > > .../devicetree/bindings/pci/qcom,pcie-ep.yaml | 160 ++++ > > MAINTAINERS | 10 +- > > drivers/pci/controller/dwc/Kconfig | 10 + > > drivers/pci/controller/dwc/Makefile | 1 + > > drivers/pci/controller/dwc/pcie-qcom-ep.c | 742 ++++++++++++++++++ > > 5 files changed, 922 insertions(+), 1 deletion(-) > > create mode 100644 Documentation/devicetree/bindings/pci/qcom,pcie-ep.yaml > > create mode 100644 drivers/pci/controller/dwc/pcie-qcom-ep.c > > > > -- > > 2.25.1 > >