From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-19.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3CBD8C47E50 for ; Wed, 14 Jul 2021 19:42:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 25AE161408 for ; Wed, 14 Jul 2021 19:42:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S233172AbhGNTpS (ORCPT ); Wed, 14 Jul 2021 15:45:18 -0400 Received: from mail.kernel.org ([198.145.29.99]:37298 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S233279AbhGNTob (ORCPT ); Wed, 14 Jul 2021 15:44:31 -0400 Received: by mail.kernel.org (Postfix) with ESMTPSA id E2E10613EF; Wed, 14 Jul 2021 19:41:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1626291675; bh=jZvXos5HbQ8tbXrwb7v67Yrm+3Nj3gPucUTCKJI5Hy0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=lrtz1kybuDjhhUaN980jwgpv7bnQJ99NvSvklVWI30B5Dq6l2gsciGab9zn6f78Zg EjtKe3SOWxb6hdhsoO7+sfezfufolLlmxaPmWGAC7qvFTG0PhlLuRBlRVil1udKqxU q7jl28Zo+tJ7NRqNlMaxcwIKJfxV+2cKtjboraO2ZFruBguRtfCy8pBS9nKtcag/Z2 +28kZwXTKYpNAJDlGoJmyJXc+BohLbX8GyuzmDf2RNzx5bUYc7R+3E4+n6z/3U0kRK hGcwJcSITXVtHkmyCxTSMbCQDRfGnhtBWgT5UkPp1qSXqK7MdmDWI+O/sru9iR2uwL 23T91pisvxLog== From: Sasha Levin To: linux-kernel@vger.kernel.org, stable@vger.kernel.org Cc: Primoz Fiser , Shawn Guo , Sasha Levin , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH AUTOSEL 5.12 027/102] ARM: dts: imx6: phyFLEX: Fix UART hardware flow control Date: Wed, 14 Jul 2021 15:39:20 -0400 Message-Id: <20210714194036.53141-27-sashal@kernel.org> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20210714194036.53141-1-sashal@kernel.org> References: <20210714194036.53141-1-sashal@kernel.org> MIME-Version: 1.0 X-stable: review X-Patchwork-Hint: Ignore Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Primoz Fiser [ Upstream commit 14cdc1f243d79e0b46be150502b7dba9c5a6bdfd ] Serial interface uart3 on phyFLEX board is capable of 5-wire connection including signals RTS and CTS for hardware flow control. Fix signals UART3_CTS_B and UART3_RTS_B padmux assignments and add missing property "uart-has-rtscts" to allow serial interface to be configured and used with the hardware flow control. Signed-off-by: Primoz Fiser Signed-off-by: Shawn Guo Signed-off-by: Sasha Levin --- arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi index f28a96fcf23e..3f262e8ebf7f 100644 --- a/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi +++ b/arch/arm/boot/dts/imx6qdl-phytec-pfla02.dtsi @@ -316,8 +316,8 @@ pinctrl_uart3: uart3grp { fsl,pins = < MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D30__UART3_RTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D31__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1 >; }; @@ -404,6 +404,7 @@ ®_soc { &uart3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; status = "disabled"; }; -- 2.30.2