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From: Yong Wu <yong.wu@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>, Rob Herring <robh+dt@kernel.org>,
	Matthias Brugger <matthias.bgg@gmail.com>,
	Will Deacon <will@kernel.org>,
	Robin Murphy <robin.murphy@arm.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
	Evan Green <evgreen@chromium.org>, Tomasz Figa <tfiga@google.com>,
	Tomasz Figa <tfiga@chromium.org>,
	<linux-mediatek@lists.infradead.org>,
	<srv_heupstream@mediatek.com>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<iommu@lists.linux-foundation.org>, <yong.wu@mediatek.com>,
	<youlin.pei@mediatek.com>,
	Nicolas Boichat <drinkcat@chromium.org>, <anan.sun@mediatek.com>,
	<chao.hao@mediatek.com>
Subject: [PATCH v2 19/29] iommu/mediatek: Add mt8195 support
Date: Fri, 13 Aug 2021 14:53:14 +0800	[thread overview]
Message-ID: <20210813065324.29220-20-yong.wu@mediatek.com> (raw)
In-Reply-To: <20210813065324.29220-1-yong.wu@mediatek.com>

mt8195 has 3 IOMMU, containing 2 MM IOMMUs, one is for vdo, the other
is for vpp. and 1 INFRA IOMMU.

Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
 drivers/iommu/mtk_iommu.c | 42 +++++++++++++++++++++++++++++++++++++++
 drivers/iommu/mtk_iommu.h |  1 +
 2 files changed, 43 insertions(+)

diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index b7a31f3a1bcf..d7eec20f0476 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -1168,6 +1168,45 @@ static const struct mtk_iommu_plat_data mt8192_data = {
 			   {0, 14, 16}, {0, 13, 18, 17}},
 };
 
+static const struct mtk_iommu_plat_data mt8195_data_infra = {
+	.m4u_plat	  = M4U_MT8195,
+	.flags            = WR_THROT_EN | DCM_DISABLE |
+			    MTK_IOMMU_TYPE_INFRA | IFA_IOMMU_PCIe_SUPPORT,
+	.pericfg_comp_str = "mediatek,mt8195-pericfg_ao",
+	.inv_sel_reg      = REG_MMU_INV_SEL_GEN2,
+	.iova_region      = single_domain,
+	.iova_region_nr   = ARRAY_SIZE(single_domain),
+};
+
+static const struct mtk_iommu_plat_data mt8195_data_vdo = {
+	.m4u_plat	= M4U_MT8195,
+	.flags          = HAS_BCLK | HAS_SUB_COMM_2BITS | OUT_ORDER_WR_EN |
+			  WR_THROT_EN | NOT_STD_AXI_MODE | IOVA_34_EN |
+			  SHARE_PGTABLE | MTK_IOMMU_TYPE_MM,
+	.hw_list        = &m4ulist,
+	.inv_sel_reg    = REG_MMU_INV_SEL_GEN2,
+	.iova_region	= mt8192_multi_dom,
+	.iova_region_nr	= ARRAY_SIZE(mt8192_multi_dom),
+	.larbid_remap   = {{2, 0}, {21}, {24}, {7}, {19}, {9, 10, 11},
+			   {13, 17, 15/* 17b */, 25}, {5}},
+};
+
+static const struct mtk_iommu_plat_data mt8195_data_vpp = {
+	.m4u_plat	= M4U_MT8195,
+	.flags          = HAS_BCLK | HAS_SUB_COMM_3BITS | OUT_ORDER_WR_EN |
+			  WR_THROT_EN | NOT_STD_AXI_MODE | IOVA_34_EN |
+			  SHARE_PGTABLE | MTK_IOMMU_TYPE_MM,
+	.hw_list        = &m4ulist,
+	.inv_sel_reg    = REG_MMU_INV_SEL_GEN2,
+	.iova_region	= mt8192_multi_dom,
+	.iova_region_nr	= ARRAY_SIZE(mt8192_multi_dom),
+	.larbid_remap   = {{1}, {3}, {22, 0, 0, 0, 23}, {8},
+			   {20}, {12},
+			   /* 16: 16a; 29: 16b; 30: CCUtop0; 31: CCUtop1 */
+			   {14, 16, 29, 26, 30, 31, 18},
+			   {4, 0, 0, 0, 6}},
+};
+
 static const struct of_device_id mtk_iommu_of_ids[] = {
 	{ .compatible = "mediatek,mt2712-m4u", .data = &mt2712_data},
 	{ .compatible = "mediatek,mt6779-m4u", .data = &mt6779_data},
@@ -1175,6 +1214,9 @@ static const struct of_device_id mtk_iommu_of_ids[] = {
 	{ .compatible = "mediatek,mt8173-m4u", .data = &mt8173_data},
 	{ .compatible = "mediatek,mt8183-m4u", .data = &mt8183_data},
 	{ .compatible = "mediatek,mt8192-m4u", .data = &mt8192_data},
+	{ .compatible = "mediatek,mt8195-iommu-infra", .data = &mt8195_data_infra},
+	{ .compatible = "mediatek,mt8195-iommu-vdo",   .data = &mt8195_data_vdo},
+	{ .compatible = "mediatek,mt8195-iommu-vpp",   .data = &mt8195_data_vpp},
 	{}
 };
 
diff --git a/drivers/iommu/mtk_iommu.h b/drivers/iommu/mtk_iommu.h
index 676d306af046..e7ede1123624 100644
--- a/drivers/iommu/mtk_iommu.h
+++ b/drivers/iommu/mtk_iommu.h
@@ -46,6 +46,7 @@ enum mtk_iommu_plat {
 	M4U_MT8173,
 	M4U_MT8183,
 	M4U_MT8192,
+	M4U_MT8195,
 };
 
 struct mtk_iommu_iova_region;
-- 
2.18.0


  parent reply	other threads:[~2021-08-13  6:56 UTC|newest]

Thread overview: 37+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-08-13  6:52 [PATCH v2 00/29] MT8195 IOMMU SUPPORT Yong Wu
2021-08-13  6:52 ` [PATCH v2 01/29] dt-bindings: mediatek: mt8195: Add binding for MM IOMMU Yong Wu
2021-08-13  6:52 ` [PATCH v2 02/29] dt-bindings: mediatek: mt8195: Add binding for infra IOMMU Yong Wu
2021-08-17 21:44   ` Rob Herring
2021-08-13  6:52 ` [PATCH v2 03/29] iommu/mediatek: Fix 2 HW sharing pgtable issue Yong Wu
2021-08-13  6:52 ` [PATCH v2 04/29] iommu/mediatek: Adapt sharing and non-sharing pgtable case Yong Wu
2021-08-13  6:53 ` [PATCH v2 05/29] iommu/mediatek: Add 12G~16G support for multi domains Yong Wu
2021-08-13  6:53 ` [PATCH v2 06/29] iommu/mediatek: Add a flag DCM_DISABLE Yong Wu
2021-08-13  6:53 ` [PATCH v2 07/29] iommu/mediatek: Add a flag NON_STD_AXI Yong Wu
2021-08-13  6:53 ` [PATCH v2 08/29] iommu/mediatek: Remove for_each_m4u in tlb_sync_all Yong Wu
2021-08-13  6:53 ` [PATCH v2 09/29] iommu/mediatek: Add tlb_lock in tlb_flush_all Yong Wu
2021-08-13  6:53 ` [PATCH v2 10/29] iommu/mediatek: Remove the granule in the tlb flush Yong Wu
2021-08-13  6:53 ` [PATCH v2 11/29] iommu/mediatek: Always pm_runtime_get while " Yong Wu
2021-08-24  7:10   ` Hsin-Yi Wang
2021-09-01 12:10     ` Yong Wu (吴勇)
2021-09-30 11:26   ` Dafna Hirschfeld
2021-10-07  3:00     ` Yong Wu
2021-08-13  6:53 ` [PATCH v2 12/29] iommu/mediatek: Always enable output PA over 32bits in isr Yong Wu
2021-08-13  6:53 ` [PATCH v2 13/29] iommu/mediatek: Add SUB_COMMON_3BITS flag Yong Wu
2021-08-13  6:53 ` [PATCH v2 14/29] iommu/mediatek: Add IOMMU_TYPE flag Yong Wu
2021-08-13  6:53 ` [PATCH v2 15/29] iommu/mediatek: Contain MM IOMMU flow with the MM TYPE Yong Wu
2021-08-13  6:53 ` [PATCH v2 16/29] iommu/mediatek: Adjust device link when it is sub-common Yong Wu
2021-08-24  7:35   ` Hsin-Yi Wang
2021-09-01 12:01     ` Yong Wu (吴勇)
2021-08-13  6:53 ` [PATCH v2 17/29] iommu/mediatek: Add infra iommu support Yong Wu
2021-08-13  6:53 ` [PATCH v2 18/29] iommu/mediatek: Add PCIe support Yong Wu
2021-08-13  6:53 ` Yong Wu [this message]
2021-08-13  6:53 ` [PATCH v2 20/29] iommu/mediatek: Only adjust code about register base Yong Wu
2021-08-13  6:53 ` [PATCH v2 21/29] iommu/mediatek: Just move code position in hw_init Yong Wu
2021-08-13  6:53 ` [PATCH v2 22/29] iommu/mediatek: Add mtk_iommu_bank_data structure Yong Wu
2021-08-13  6:53 ` [PATCH v2 23/29] iommu/mediatek: Initialise bank HW for each a bank Yong Wu
2021-08-13  6:53 ` [PATCH v2 24/29] iommu/mediatek: Add bank_nr and bank_enable Yong Wu
2021-08-13  6:53 ` [PATCH v2 25/29] iommu/mediatek: Change the domid to iova_region_id Yong Wu
2021-08-13  6:53 ` [PATCH v2 26/29] iommu/mediatek: Get the proper bankid for multi banks Yong Wu
2021-08-13  6:53 ` [PATCH v2 27/29] iommu/mediatek: Initialise/Remove for multi bank dev Yong Wu
2021-08-13  6:53 ` [PATCH v2 28/29] iommu/mediatek: Backup/restore regsiters for multi banks Yong Wu
2021-08-13  6:53 ` [PATCH v2 29/29] iommu/mediatek: mt8195: Enable multi banks for infra iommu Yong Wu

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