From: Yong Wu <yong.wu@mediatek.com>
To: Joerg Roedel <joro@8bytes.org>, Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
Evan Green <evgreen@chromium.org>, Tomasz Figa <tfiga@google.com>,
Tomasz Figa <tfiga@chromium.org>,
<linux-mediatek@lists.infradead.org>,
<srv_heupstream@mediatek.com>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<iommu@lists.linux-foundation.org>, <yong.wu@mediatek.com>,
<youlin.pei@mediatek.com>,
Nicolas Boichat <drinkcat@chromium.org>, <anan.sun@mediatek.com>,
<chao.hao@mediatek.com>
Subject: [PATCH v2 07/29] iommu/mediatek: Add a flag NON_STD_AXI
Date: Fri, 13 Aug 2021 14:53:02 +0800 [thread overview]
Message-ID: <20210813065324.29220-8-yong.wu@mediatek.com> (raw)
In-Reply-To: <20210813065324.29220-1-yong.wu@mediatek.com>
Add a new flag NON_STD_AXI, All the previous SoC support this flag.
Prepare for adding infra and apu iommu which don't support this.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
---
drivers/iommu/mtk_iommu.c | 16 ++++++++++------
1 file changed, 10 insertions(+), 6 deletions(-)
diff --git a/drivers/iommu/mtk_iommu.c b/drivers/iommu/mtk_iommu.c
index bd50f3020bc1..175065b76509 100644
--- a/drivers/iommu/mtk_iommu.c
+++ b/drivers/iommu/mtk_iommu.c
@@ -123,6 +123,7 @@
#define IOVA_34_EN BIT(8)
#define SHARE_PGTABLE BIT(9) /* 2 HW share pgtable */
#define DCM_DISABLE BIT(10)
+#define NOT_STD_AXI_MODE BIT(11)
#define MTK_IOMMU_HAS_FLAG(pdata, _x) \
((((pdata)->flags) & (_x)) == (_x))
@@ -753,7 +754,8 @@ static int mtk_iommu_hw_init(const struct mtk_iommu_data *data)
regval = 0;
} else {
regval = readl_relaxed(data->base + REG_MMU_MISC_CTRL);
- regval &= ~F_MMU_STANDARD_AXI_MODE_MASK;
+ if (MTK_IOMMU_HAS_FLAG(data->plat_data, NOT_STD_AXI_MODE))
+ regval &= ~F_MMU_STANDARD_AXI_MODE_MASK;
if (MTK_IOMMU_HAS_FLAG(data->plat_data, OUT_ORDER_WR_EN))
regval &= ~F_MMU_IN_ORDER_WR_EN_MASK;
}
@@ -1016,7 +1018,8 @@ static const struct dev_pm_ops mtk_iommu_pm_ops = {
static const struct mtk_iommu_plat_data mt2712_data = {
.m4u_plat = M4U_MT2712,
- .flags = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG | SHARE_PGTABLE,
+ .flags = HAS_4GB_MODE | HAS_BCLK | HAS_VLD_PA_RNG | SHARE_PGTABLE |
+ NOT_STD_AXI_MODE,
.hw_list = &m4ulist,
.inv_sel_reg = REG_MMU_INV_SEL_GEN1,
.iova_region = single_domain,
@@ -1026,7 +1029,8 @@ static const struct mtk_iommu_plat_data mt2712_data = {
static const struct mtk_iommu_plat_data mt6779_data = {
.m4u_plat = M4U_MT6779,
- .flags = HAS_SUB_COMM | OUT_ORDER_WR_EN | WR_THROT_EN,
+ .flags = HAS_SUB_COMM | OUT_ORDER_WR_EN | WR_THROT_EN |
+ NOT_STD_AXI_MODE,
.inv_sel_reg = REG_MMU_INV_SEL_GEN2,
.iova_region = single_domain,
.iova_region_nr = ARRAY_SIZE(single_domain),
@@ -1035,7 +1039,7 @@ static const struct mtk_iommu_plat_data mt6779_data = {
static const struct mtk_iommu_plat_data mt8167_data = {
.m4u_plat = M4U_MT8167,
- .flags = RESET_AXI | HAS_LEGACY_IVRP_PADDR,
+ .flags = RESET_AXI | HAS_LEGACY_IVRP_PADDR | NOT_STD_AXI_MODE,
.inv_sel_reg = REG_MMU_INV_SEL_GEN1,
.iova_region = single_domain,
.iova_region_nr = ARRAY_SIZE(single_domain),
@@ -1045,7 +1049,7 @@ static const struct mtk_iommu_plat_data mt8167_data = {
static const struct mtk_iommu_plat_data mt8173_data = {
.m4u_plat = M4U_MT8173,
.flags = HAS_4GB_MODE | HAS_BCLK | RESET_AXI |
- HAS_LEGACY_IVRP_PADDR,
+ HAS_LEGACY_IVRP_PADDR | NOT_STD_AXI_MODE,
.inv_sel_reg = REG_MMU_INV_SEL_GEN1,
.iova_region = single_domain,
.iova_region_nr = ARRAY_SIZE(single_domain),
@@ -1064,7 +1068,7 @@ static const struct mtk_iommu_plat_data mt8183_data = {
static const struct mtk_iommu_plat_data mt8192_data = {
.m4u_plat = M4U_MT8192,
.flags = HAS_BCLK | HAS_SUB_COMM | OUT_ORDER_WR_EN |
- WR_THROT_EN | IOVA_34_EN,
+ WR_THROT_EN | IOVA_34_EN | NOT_STD_AXI_MODE,
.inv_sel_reg = REG_MMU_INV_SEL_GEN2,
.iova_region = mt8192_multi_dom,
.iova_region_nr = ARRAY_SIZE(mt8192_multi_dom),
--
2.18.0
next prev parent reply other threads:[~2021-08-13 6:54 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-13 6:52 [PATCH v2 00/29] MT8195 IOMMU SUPPORT Yong Wu
2021-08-13 6:52 ` [PATCH v2 01/29] dt-bindings: mediatek: mt8195: Add binding for MM IOMMU Yong Wu
2021-08-13 6:52 ` [PATCH v2 02/29] dt-bindings: mediatek: mt8195: Add binding for infra IOMMU Yong Wu
2021-08-17 21:44 ` Rob Herring
2021-08-13 6:52 ` [PATCH v2 03/29] iommu/mediatek: Fix 2 HW sharing pgtable issue Yong Wu
2021-08-13 6:52 ` [PATCH v2 04/29] iommu/mediatek: Adapt sharing and non-sharing pgtable case Yong Wu
2021-08-13 6:53 ` [PATCH v2 05/29] iommu/mediatek: Add 12G~16G support for multi domains Yong Wu
2021-08-13 6:53 ` [PATCH v2 06/29] iommu/mediatek: Add a flag DCM_DISABLE Yong Wu
2021-08-13 6:53 ` Yong Wu [this message]
2021-08-13 6:53 ` [PATCH v2 08/29] iommu/mediatek: Remove for_each_m4u in tlb_sync_all Yong Wu
2021-08-13 6:53 ` [PATCH v2 09/29] iommu/mediatek: Add tlb_lock in tlb_flush_all Yong Wu
2021-08-13 6:53 ` [PATCH v2 10/29] iommu/mediatek: Remove the granule in the tlb flush Yong Wu
2021-08-13 6:53 ` [PATCH v2 11/29] iommu/mediatek: Always pm_runtime_get while " Yong Wu
2021-08-24 7:10 ` Hsin-Yi Wang
2021-09-01 12:10 ` Yong Wu (吴勇)
2021-09-30 11:26 ` Dafna Hirschfeld
2021-10-07 3:00 ` Yong Wu
2021-08-13 6:53 ` [PATCH v2 12/29] iommu/mediatek: Always enable output PA over 32bits in isr Yong Wu
2021-08-13 6:53 ` [PATCH v2 13/29] iommu/mediatek: Add SUB_COMMON_3BITS flag Yong Wu
2021-08-13 6:53 ` [PATCH v2 14/29] iommu/mediatek: Add IOMMU_TYPE flag Yong Wu
2021-08-13 6:53 ` [PATCH v2 15/29] iommu/mediatek: Contain MM IOMMU flow with the MM TYPE Yong Wu
2021-08-13 6:53 ` [PATCH v2 16/29] iommu/mediatek: Adjust device link when it is sub-common Yong Wu
2021-08-24 7:35 ` Hsin-Yi Wang
2021-09-01 12:01 ` Yong Wu (吴勇)
2021-08-13 6:53 ` [PATCH v2 17/29] iommu/mediatek: Add infra iommu support Yong Wu
2021-08-13 6:53 ` [PATCH v2 18/29] iommu/mediatek: Add PCIe support Yong Wu
2021-08-13 6:53 ` [PATCH v2 19/29] iommu/mediatek: Add mt8195 support Yong Wu
2021-08-13 6:53 ` [PATCH v2 20/29] iommu/mediatek: Only adjust code about register base Yong Wu
2021-08-13 6:53 ` [PATCH v2 21/29] iommu/mediatek: Just move code position in hw_init Yong Wu
2021-08-13 6:53 ` [PATCH v2 22/29] iommu/mediatek: Add mtk_iommu_bank_data structure Yong Wu
2021-08-13 6:53 ` [PATCH v2 23/29] iommu/mediatek: Initialise bank HW for each a bank Yong Wu
2021-08-13 6:53 ` [PATCH v2 24/29] iommu/mediatek: Add bank_nr and bank_enable Yong Wu
2021-08-13 6:53 ` [PATCH v2 25/29] iommu/mediatek: Change the domid to iova_region_id Yong Wu
2021-08-13 6:53 ` [PATCH v2 26/29] iommu/mediatek: Get the proper bankid for multi banks Yong Wu
2021-08-13 6:53 ` [PATCH v2 27/29] iommu/mediatek: Initialise/Remove for multi bank dev Yong Wu
2021-08-13 6:53 ` [PATCH v2 28/29] iommu/mediatek: Backup/restore regsiters for multi banks Yong Wu
2021-08-13 6:53 ` [PATCH v2 29/29] iommu/mediatek: mt8195: Enable multi banks for infra iommu Yong Wu
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