[RFC PATCH v3 net-next 10/10] docs: devicetree: add documentation for the VSC7512 SPI device

Colin Foster
2021-08-14T02:50:38Z

Signed-off-by: Colin Foster <colin.foster@in-advantage.com>
---
.../devicetree/bindings/net/dsa/ocelot.txt | 92 +++++++++++++++++++
1 file changed, 92 insertions(+)

diff --git a/Documentation/devicetree/bindings/net/dsa/ocelot.txt b/Documentation/devicetree/bindings/net/dsa/ocelot.txt
index 7a271d070b72..edf560a50803 100644
--- a/Documentation/devicetree/bindings/net/dsa/ocelot.txt
+++ b/Documentation/devicetree/bindings/net/dsa/ocelot.txt
@@ -8,6 +8,7 @@ Currently the switches supported by the felix driver are:

- VSC9959 (Felix)
- VSC9953 (Seville)
+- VSC7511, VSC7512, VSC7513, VSC7514 via SPI

The VSC9959 switch is found in the NXP LS1028A. It is a PCI device, part of the
larger ENETC root complex. As a result, the ethernet-switch node is a sub-node
@@ -211,3 +212,94 @@ Example:
};
};
};
+
+The VSC7513 and VSC7514 switches can be controlled internally via the MIPS
+processor. The VSC7511 and VSC7512 don't have this internal processor, but all
+four chips can be controlled externally through SPI with the following required
+properties:
+
+- compatible:
+ Can be "mscc,vsc7511", "mscc,vsc7512", "mscc,vsc7513", or
+ "mscc,vsc7514".
+
+Supported phy modes for all chips are:
+
+* phy_mode = "sgmii": on ports 0, 1, 2, 3
+
+The VSC7512 and 7514 also support:
+
+* phy_mode = "sgmii": on ports 4, 5, 6, 7
+* phy_mode = "qsgmii": on ports 7, 8, 10
+
+Example for control from a BeagleBone Black
+
+&spi0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ ethernet-switch@0 {
+ compatible = "mscc,vsc7512";
+ spi-max-frequency = <250000>;
+ reg = <0>;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@0 {
+ reg = <0>;
+ ethernet = <&mac>;
+ phy-mode = "sgmii";
+
+ fixed-link {
+ speed = <100>;
+ full-duplex;
+ };
+ };
+
+ port@1 {
+ reg = <1>;
+ label = "swp1";
+ phy-handle = <&sw_phy1>;
+ phy-mode = "sgmii";
+ };
+
+ port@2 {
+ reg = <2>;
+ label = "swp2";
+ phy-handle = <&sw_phy2>;
+ phy-mode = "sgmii";
+ };
+
+ port@3 {
+ reg = <3>;
+ label = "swp3";
+ phy-handle = <&sw_phy3>;
+ phy-mode = "sgmii";
+ };
+ };
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ sw_phy1: ethernet-phy@1 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x1>;
+ };
+
+ sw_phy2: ethernet-phy@2 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x2>;
+ };
+
+ sw_phy3: ethernet-phy@3 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x3>;
+ };
+ };
+ };
+};
--
2.25.1