From: Claudiu Beznea <claudiu.beznea@microchip.com>
To: <nicolas.ferre@microchip.com>, <alexandre.belloni@bootlin.com>,
<ludovic.desroches@microchip.com>, <robh+dt@kernel.org>
Cc: <linux-arm-kernel@lists.infradead.org>,
<devicetree@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
Claudiu Beznea <claudiu.beznea@microchip.com>
Subject: [PATCH 2/3] ARM: dts: at91: add bindins for securam
Date: Mon, 23 Aug 2021 13:03:55 +0300 [thread overview]
Message-ID: <20210823100356.22206-3-claudiu.beznea@microchip.com> (raw)
In-Reply-To: <20210823100356.22206-1-claudiu.beznea@microchip.com>
Add bindings for securam.
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
---
arch/arm/boot/dts/sama7g5.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/sama7g5.dtsi b/arch/arm/boot/dts/sama7g5.dtsi
index ecabab4343b6..3a4315ac0eb0 100644
--- a/arch/arm/boot/dts/sama7g5.dtsi
+++ b/arch/arm/boot/dts/sama7g5.dtsi
@@ -75,6 +75,17 @@ soc {
#size-cells = <1>;
ranges;
+ securam: securam@e0000000 {
+ compatible = "microchip,sama7g5-securam", "atmel,sama5d2-securam", "mmio-sram";
+ reg = <0xe0000000 0x4000>;
+ clocks = <&pmc PMC_TYPE_PERIPHERAL 18>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0xe0000000 0x4000>;
+ no-memory-wc;
+ status = "okay";
+ };
+
secumod: secumod@e0004000 {
compatible = "microchip,sama7g5-secumod", "atmel,sama5d2-secumod", "syscon";
reg = <0xe0004000 0x4000>;
--
2.25.1
next prev parent reply other threads:[~2021-08-23 10:04 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-23 10:03 [PATCH 0/3] ARM: dts: at91: enable ips for sama7g5 Claudiu Beznea
2021-08-23 10:03 ` [PATCH 1/3] ARM: dts: at91: add ram bindings Claudiu Beznea
2021-08-23 10:03 ` Claudiu Beznea [this message]
2021-08-23 10:03 ` [PATCH 3/3] ARM: dts: at91: add bindings for shdwc Claudiu Beznea
2021-08-23 12:18 ` [PATCH 0/3] ARM: dts: at91: enable ips for sama7g5 Alexandre Belloni
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