From: Chun-Jie Chen <chun-jie.chen@mediatek.com>
To: Matthias Brugger <matthias.bgg@gmail.com>,
Rob Herring <robh+dt@kernel.org>,
Nicolas Boichat <drinkcat@chromium.org>
Cc: <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
<linux-mediatek@lists.infradead.org>,
<srv_heupstream@mediatek.com>,
<Project_Global_Chrome_Upstream_Group@mediatek.com>,
Chun-Jie Chen <chun-jie.chen@mediatek.com>
Subject: [v1 5/5] arm64: dts: mediatek: Correct I2C clock of MT8192
Date: Wed, 25 Aug 2021 09:11:20 +0800 [thread overview]
Message-ID: <20210825011120.30481-6-chun-jie.chen@mediatek.com> (raw)
In-Reply-To: <20210825011120.30481-1-chun-jie.chen@mediatek.com>
update i2c 0 ~ 9 clocks to the real ones.
Signed-off-by: Chun-Jie Chen <chun-jie.chen@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 30 ++++++++++++++++--------
1 file changed, 20 insertions(+), 10 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index db6f4c6dc404..866b04e78690 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -484,7 +484,8 @@
reg = <0 0x11cb0000 0 0x1000>,
<0 0x10217300 0 0x80>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_e CLK_IMP_IIC_WRAP_E_I2C3>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -503,7 +504,8 @@
reg = <0 0x11d00000 0 0x1000>,
<0 0x10217600 0 0x180>;
interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -516,7 +518,8 @@
reg = <0 0x11d01000 0 0x1000>,
<0 0x10217780 0 0x180>;
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C8>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -529,7 +532,8 @@
reg = <0 0x11d02000 0 0x1000>,
<0 0x10217900 0 0x180>;
interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C9>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -548,7 +552,8 @@
reg = <0 0x11d20000 0 0x1000>,
<0 0x10217100 0 0x80>;
interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C1>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -561,7 +566,8 @@
reg = <0 0x11d21000 0 0x1000>,
<0 0x10217180 0 0x180>;
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C2>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -574,7 +580,8 @@
reg = <0 0x11d22000 0 0x1000>,
<0 0x10217380 0 0x180>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_ws CLK_IMP_IIC_WRAP_WS_I2C4>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -593,7 +600,8 @@
reg = <0 0x11e00000 0 0x1000>,
<0 0x10217500 0 0x80>;
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C5>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -612,7 +620,8 @@
reg = <0 0x11f00000 0 0x1000>,
<0 0x10217080 0 0x80>;
interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C0>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
@@ -625,7 +634,8 @@
reg = <0 0x11f01000 0 0x1000>,
<0 0x10217580 0 0x80>;
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH 0>;
- clocks = <&clk26m>, <&clk26m>;
+ clocks = <&imp_iic_wrap_n CLK_IMP_IIC_WRAP_N_I2C6>,
+ <&infracfg CLK_INFRA_AP_DMA>;
clock-names = "main", "dma";
clock-div = <1>;
#address-cells = <1>;
--
2.18.0
next prev parent reply other threads:[~2021-08-25 1:12 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <20210825011120.30481-1-chun-jie.chen@mediatek.com>
2021-08-25 1:11 ` [v1 1/5] arm64: dts: mediatek: Correct system timer clock of MT8192 Chun-Jie Chen
2021-12-06 16:41 ` Nícolas F. R. A. Prado
2021-08-25 1:11 ` [v1 2/5] arm64: dts: mediatek: Correct UART " Chun-Jie Chen
2021-12-06 16:44 ` Nícolas F. R. A. Prado
2021-08-25 1:11 ` [v1 3/5] arm64: dts: mediatek: Correct SPI " Chun-Jie Chen
2021-12-06 16:47 ` Nícolas F. R. A. Prado
2021-08-25 1:11 ` [v1 4/5] arm64: dts: mediatek: Correct Nor Flash " Chun-Jie Chen
2021-12-06 16:48 ` Nícolas F. R. A. Prado
2021-08-25 1:11 ` Chun-Jie Chen [this message]
2021-12-06 16:49 ` [v1 5/5] arm64: dts: mediatek: Correct I2C " Nícolas F. R. A. Prado
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