* [PATCH 1/2] dt-bindings: coresight: Add burst size for TMC
2021-09-01 13:10 [PATCH 0/2] coresight: tmc: Add support to configure AXI burst size Tanmay Jagdale
@ 2021-09-01 13:10 ` Tanmay Jagdale
2021-09-02 16:27 ` Mike Leach
2021-09-03 19:54 ` Rob Herring
2021-09-01 13:10 ` [PATCH 2/2] coresight: tmc: Configure AXI write burst size Tanmay Jagdale
` (2 subsequent siblings)
3 siblings, 2 replies; 8+ messages in thread
From: Tanmay Jagdale @ 2021-09-01 13:10 UTC (permalink / raw)
To: mathieu.poirier, suzuki.poulose, mike.leach, leo.yan, robh+dt
Cc: coresight, linux-arm-kernel, devicetree, al.grant, sgoutham,
lcherian, bbhushan2, Tanmay Jagdale
Add "arm,max-burst-size" optional property for TMC ETR.
If specified, this value indicates the maximum burst size
that can be initiated by TMC on the AXI bus.
Signed-off-by: Tanmay Jagdale <tanmay@marvell.com>
---
Documentation/devicetree/bindings/arm/coresight.txt | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
index 7f9c1ca87487..7971f8dba2ee 100644
--- a/Documentation/devicetree/bindings/arm/coresight.txt
+++ b/Documentation/devicetree/bindings/arm/coresight.txt
@@ -127,6 +127,11 @@ its hardware characteristcs.
* arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely
use the SG mode on this system.
+ * arm,max-burst-size: The maximum burst size initiated by TMC on the
+ AXI master interface. The burst size can be in the range [0..15],
+ the setting supports one data transfer per burst upto a maximum of
+ 16 data transfers per burst.
+
* Optional property for CATU :
* interrupts : Exactly one SPI may be listed for reporting the address
error
--
2.25.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH 1/2] dt-bindings: coresight: Add burst size for TMC
2021-09-01 13:10 ` [PATCH 1/2] dt-bindings: coresight: Add burst size for TMC Tanmay Jagdale
@ 2021-09-02 16:27 ` Mike Leach
2021-09-03 19:54 ` Rob Herring
1 sibling, 0 replies; 8+ messages in thread
From: Mike Leach @ 2021-09-02 16:27 UTC (permalink / raw)
To: Tanmay Jagdale
Cc: Mathieu Poirier, Suzuki K. Poulose, Leo Yan, Rob Herring,
Coresight ML, linux-arm-kernel, devicetree, Al Grant,
Sunil Kovvuri Goutham, Linu Cherian, Bharat Bhushan
On Wed, 1 Sept 2021 at 14:12, Tanmay Jagdale <tanmay@marvell.com> wrote:
>
> Add "arm,max-burst-size" optional property for TMC ETR.
> If specified, this value indicates the maximum burst size
> that can be initiated by TMC on the AXI bus.
>
> Signed-off-by: Tanmay Jagdale <tanmay@marvell.com>
> ---
> Documentation/devicetree/bindings/arm/coresight.txt | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/arm/coresight.txt b/Documentation/devicetree/bindings/arm/coresight.txt
> index 7f9c1ca87487..7971f8dba2ee 100644
> --- a/Documentation/devicetree/bindings/arm/coresight.txt
> +++ b/Documentation/devicetree/bindings/arm/coresight.txt
> @@ -127,6 +127,11 @@ its hardware characteristcs.
> * arm,scatter-gather: boolean. Indicates that the TMC-ETR can safely
> use the SG mode on this system.
>
> + * arm,max-burst-size: The maximum burst size initiated by TMC on the
> + AXI master interface. The burst size can be in the range [0..15],
> + the setting supports one data transfer per burst upto a maximum of
> + 16 data transfers per burst.
> +
> * Optional property for CATU :
> * interrupts : Exactly one SPI may be listed for reporting the address
> error
> --
> 2.25.1
>
Reviewed-by: Mike Leach <mike.leach@linaro.org>
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] dt-bindings: coresight: Add burst size for TMC
2021-09-01 13:10 ` [PATCH 1/2] dt-bindings: coresight: Add burst size for TMC Tanmay Jagdale
2021-09-02 16:27 ` Mike Leach
@ 2021-09-03 19:54 ` Rob Herring
1 sibling, 0 replies; 8+ messages in thread
From: Rob Herring @ 2021-09-03 19:54 UTC (permalink / raw)
To: Tanmay Jagdale
Cc: linux-arm-kernel, lcherian, bbhushan2, coresight, devicetree,
suzuki.poulose, leo.yan, robh+dt, al.grant, mike.leach, sgoutham,
mathieu.poirier
On Wed, 01 Sep 2021 18:40:48 +0530, Tanmay Jagdale wrote:
> Add "arm,max-burst-size" optional property for TMC ETR.
> If specified, this value indicates the maximum burst size
> that can be initiated by TMC on the AXI bus.
>
> Signed-off-by: Tanmay Jagdale <tanmay@marvell.com>
> ---
> Documentation/devicetree/bindings/arm/coresight.txt | 5 +++++
> 1 file changed, 5 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH 2/2] coresight: tmc: Configure AXI write burst size
2021-09-01 13:10 [PATCH 0/2] coresight: tmc: Add support to configure AXI burst size Tanmay Jagdale
2021-09-01 13:10 ` [PATCH 1/2] dt-bindings: coresight: Add burst size for TMC Tanmay Jagdale
@ 2021-09-01 13:10 ` Tanmay Jagdale
2021-09-02 16:29 ` Mike Leach
2021-09-02 16:32 ` [PATCH 0/2] coresight: tmc: Add support to configure AXI " Mike Leach
2021-09-07 17:17 ` Mathieu Poirier
3 siblings, 1 reply; 8+ messages in thread
From: Tanmay Jagdale @ 2021-09-01 13:10 UTC (permalink / raw)
To: mathieu.poirier, suzuki.poulose, mike.leach, leo.yan, robh+dt
Cc: coresight, linux-arm-kernel, devicetree, al.grant, sgoutham,
lcherian, bbhushan2, Tanmay Jagdale
The current driver sets the write burst size initiated by TMC-ETR on
AXI bus to a fixed value of 16. Make this configurable by reading the
value specified in fwnode. If not specified, then default to 16.
Introduced a "max_burst_size" variable in tmc_drvdata structure to
facilitate this change.
Signed-off-by: Tanmay Jagdale <tanmay@marvell.com>
---
.../hwtracing/coresight/coresight-tmc-core.c | 21 +++++++++++++++++--
.../hwtracing/coresight/coresight-tmc-etr.c | 3 ++-
drivers/hwtracing/coresight/coresight-tmc.h | 6 +++++-
3 files changed, 26 insertions(+), 4 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c
index 74c6323d4d6a..d0276af82494 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-core.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-core.c
@@ -432,6 +432,21 @@ static u32 tmc_etr_get_default_buffer_size(struct device *dev)
return size;
}
+static u32 tmc_etr_get_max_burst_size(struct device *dev)
+{
+ u32 burst_size;
+
+ if (fwnode_property_read_u32(dev->fwnode, "arm,max-burst-size",
+ &burst_size))
+ return TMC_AXICTL_WR_BURST_16;
+
+ /* Only permissible values are 0 to 15 */
+ if (burst_size > 0xF)
+ burst_size = TMC_AXICTL_WR_BURST_16;
+
+ return burst_size;
+}
+
static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
{
int ret = 0;
@@ -469,10 +484,12 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
/* This device is not associated with a session */
drvdata->pid = -1;
- if (drvdata->config_type == TMC_CONFIG_TYPE_ETR)
+ if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
drvdata->size = tmc_etr_get_default_buffer_size(dev);
- else
+ drvdata->max_burst_size = tmc_etr_get_max_burst_size(dev);
+ } else {
drvdata->size = readl_relaxed(drvdata->base + TMC_RSZ) * 4;
+ }
desc.dev = dev;
desc.groups = coresight_tmc_groups;
diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
index acdb59e0e661..0ac2a611110b 100644
--- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
+++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
@@ -982,7 +982,8 @@ static void __tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
axictl = readl_relaxed(drvdata->base + TMC_AXICTL);
axictl &= ~TMC_AXICTL_CLEAR_MASK;
- axictl |= (TMC_AXICTL_PROT_CTL_B1 | TMC_AXICTL_WR_BURST_16);
+ axictl |= TMC_AXICTL_PROT_CTL_B1;
+ axictl |= TMC_AXICTL_WR_BURST(drvdata->max_burst_size);
axictl |= TMC_AXICTL_AXCACHE_OS;
if (tmc_etr_has_cap(drvdata, TMC_ETR_AXI_ARCACHE)) {
diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
index b91ec7dde7bc..6bec20a392b3 100644
--- a/drivers/hwtracing/coresight/coresight-tmc.h
+++ b/drivers/hwtracing/coresight/coresight-tmc.h
@@ -70,7 +70,8 @@
#define TMC_AXICTL_PROT_CTL_B0 BIT(0)
#define TMC_AXICTL_PROT_CTL_B1 BIT(1)
#define TMC_AXICTL_SCT_GAT_MODE BIT(7)
-#define TMC_AXICTL_WR_BURST_16 0xF00
+#define TMC_AXICTL_WR_BURST(v) (((v) & 0xf) << 8)
+#define TMC_AXICTL_WR_BURST_16 0xf
/* Write-back Read and Write-allocate */
#define TMC_AXICTL_AXCACHE_OS (0xf << 2)
#define TMC_AXICTL_ARCACHE_OS (0xf << 16)
@@ -174,6 +175,8 @@ struct etr_buf {
* @etr_buf: details of buffer used in TMC-ETR
* @len: size of the available trace for ETF/ETB.
* @size: trace buffer size for this TMC (common for all modes).
+ * @max_burst_size: The maximum burst size that can be initiated by
+ * TMC-ETR on AXI bus.
* @mode: how this TMC is being used.
* @config_type: TMC variant, must be of type @tmc_config_type.
* @memwidth: width of the memory interface databus, in bytes.
@@ -198,6 +201,7 @@ struct tmc_drvdata {
};
u32 len;
u32 size;
+ u32 max_burst_size;
u32 mode;
enum tmc_config_type config_type;
enum tmc_mem_intf_width memwidth;
--
2.25.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH 2/2] coresight: tmc: Configure AXI write burst size
2021-09-01 13:10 ` [PATCH 2/2] coresight: tmc: Configure AXI write burst size Tanmay Jagdale
@ 2021-09-02 16:29 ` Mike Leach
0 siblings, 0 replies; 8+ messages in thread
From: Mike Leach @ 2021-09-02 16:29 UTC (permalink / raw)
To: Tanmay Jagdale
Cc: Mathieu Poirier, Suzuki K. Poulose, Leo Yan, Rob Herring,
Coresight ML, linux-arm-kernel, devicetree, Al Grant,
Sunil Kovvuri Goutham, Linu Cherian, Bharat Bhushan
On Wed, 1 Sept 2021 at 14:12, Tanmay Jagdale <tanmay@marvell.com> wrote:
>
> The current driver sets the write burst size initiated by TMC-ETR on
> AXI bus to a fixed value of 16. Make this configurable by reading the
> value specified in fwnode. If not specified, then default to 16.
>
> Introduced a "max_burst_size" variable in tmc_drvdata structure to
> facilitate this change.
>
> Signed-off-by: Tanmay Jagdale <tanmay@marvell.com>
> ---
> .../hwtracing/coresight/coresight-tmc-core.c | 21 +++++++++++++++++--
> .../hwtracing/coresight/coresight-tmc-etr.c | 3 ++-
> drivers/hwtracing/coresight/coresight-tmc.h | 6 +++++-
> 3 files changed, 26 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-tmc-core.c b/drivers/hwtracing/coresight/coresight-tmc-core.c
> index 74c6323d4d6a..d0276af82494 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc-core.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc-core.c
> @@ -432,6 +432,21 @@ static u32 tmc_etr_get_default_buffer_size(struct device *dev)
> return size;
> }
>
> +static u32 tmc_etr_get_max_burst_size(struct device *dev)
> +{
> + u32 burst_size;
> +
> + if (fwnode_property_read_u32(dev->fwnode, "arm,max-burst-size",
> + &burst_size))
> + return TMC_AXICTL_WR_BURST_16;
> +
> + /* Only permissible values are 0 to 15 */
> + if (burst_size > 0xF)
> + burst_size = TMC_AXICTL_WR_BURST_16;
> +
> + return burst_size;
> +}
> +
> static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
> {
> int ret = 0;
> @@ -469,10 +484,12 @@ static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
> /* This device is not associated with a session */
> drvdata->pid = -1;
>
> - if (drvdata->config_type == TMC_CONFIG_TYPE_ETR)
> + if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
> drvdata->size = tmc_etr_get_default_buffer_size(dev);
> - else
> + drvdata->max_burst_size = tmc_etr_get_max_burst_size(dev);
> + } else {
> drvdata->size = readl_relaxed(drvdata->base + TMC_RSZ) * 4;
> + }
>
> desc.dev = dev;
> desc.groups = coresight_tmc_groups;
> diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
> index acdb59e0e661..0ac2a611110b 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
> @@ -982,7 +982,8 @@ static void __tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
>
> axictl = readl_relaxed(drvdata->base + TMC_AXICTL);
> axictl &= ~TMC_AXICTL_CLEAR_MASK;
> - axictl |= (TMC_AXICTL_PROT_CTL_B1 | TMC_AXICTL_WR_BURST_16);
> + axictl |= TMC_AXICTL_PROT_CTL_B1;
> + axictl |= TMC_AXICTL_WR_BURST(drvdata->max_burst_size);
> axictl |= TMC_AXICTL_AXCACHE_OS;
>
> if (tmc_etr_has_cap(drvdata, TMC_ETR_AXI_ARCACHE)) {
> diff --git a/drivers/hwtracing/coresight/coresight-tmc.h b/drivers/hwtracing/coresight/coresight-tmc.h
> index b91ec7dde7bc..6bec20a392b3 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc.h
> +++ b/drivers/hwtracing/coresight/coresight-tmc.h
> @@ -70,7 +70,8 @@
> #define TMC_AXICTL_PROT_CTL_B0 BIT(0)
> #define TMC_AXICTL_PROT_CTL_B1 BIT(1)
> #define TMC_AXICTL_SCT_GAT_MODE BIT(7)
> -#define TMC_AXICTL_WR_BURST_16 0xF00
> +#define TMC_AXICTL_WR_BURST(v) (((v) & 0xf) << 8)
> +#define TMC_AXICTL_WR_BURST_16 0xf
> /* Write-back Read and Write-allocate */
> #define TMC_AXICTL_AXCACHE_OS (0xf << 2)
> #define TMC_AXICTL_ARCACHE_OS (0xf << 16)
> @@ -174,6 +175,8 @@ struct etr_buf {
> * @etr_buf: details of buffer used in TMC-ETR
> * @len: size of the available trace for ETF/ETB.
> * @size: trace buffer size for this TMC (common for all modes).
> + * @max_burst_size: The maximum burst size that can be initiated by
> + * TMC-ETR on AXI bus.
> * @mode: how this TMC is being used.
> * @config_type: TMC variant, must be of type @tmc_config_type.
> * @memwidth: width of the memory interface databus, in bytes.
> @@ -198,6 +201,7 @@ struct tmc_drvdata {
> };
> u32 len;
> u32 size;
> + u32 max_burst_size;
> u32 mode;
> enum tmc_config_type config_type;
> enum tmc_mem_intf_width memwidth;
> --
> 2.25.1
>
Reviewed-by: Mike Leach <mike.leach@linaro.org>
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 0/2] coresight: tmc: Add support to configure AXI burst size
2021-09-01 13:10 [PATCH 0/2] coresight: tmc: Add support to configure AXI burst size Tanmay Jagdale
2021-09-01 13:10 ` [PATCH 1/2] dt-bindings: coresight: Add burst size for TMC Tanmay Jagdale
2021-09-01 13:10 ` [PATCH 2/2] coresight: tmc: Configure AXI write burst size Tanmay Jagdale
@ 2021-09-02 16:32 ` Mike Leach
2021-09-07 17:17 ` Mathieu Poirier
3 siblings, 0 replies; 8+ messages in thread
From: Mike Leach @ 2021-09-02 16:32 UTC (permalink / raw)
To: Tanmay Jagdale
Cc: Mathieu Poirier, Suzuki K. Poulose, Leo Yan, Rob Herring,
Coresight ML, linux-arm-kernel, devicetree, Al Grant,
Sunil Kovvuri Goutham, Linu Cherian, Bharat Bhushan
Hi
Looks good from a driver / hw perspective.
As long as the device tree people are happy with the binding then this
set seems OK to me.
Regards
Mike
On Wed, 1 Sept 2021 at 14:11, Tanmay Jagdale <tanmay@marvell.com> wrote:
>
> Add a new device tree parameter, "arm,max-burst-size" to configure
> the max burst size that can be initiated by TMC-ETR on the AXI bus.
>
> Also add description of this property in coresight documentation.
>
> This patch series applies on top of the coresight next branch [1].
> https://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git/log/?h=next
>
> Tanmay Jagdale (2):
> dt-bindings: coresight: Add burst size for TMC
> coresight: tmc: Configure AXI write burst size
>
> .../devicetree/bindings/arm/coresight.txt | 5 +++++
> .../hwtracing/coresight/coresight-tmc-core.c | 21 +++++++++++++++++--
> .../hwtracing/coresight/coresight-tmc-etr.c | 3 ++-
> drivers/hwtracing/coresight/coresight-tmc.h | 6 +++++-
> 4 files changed, 31 insertions(+), 4 deletions(-)
>
> --
> 2.25.1
>
--
Mike Leach
Principal Engineer, ARM Ltd.
Manchester Design Centre. UK
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 0/2] coresight: tmc: Add support to configure AXI burst size
2021-09-01 13:10 [PATCH 0/2] coresight: tmc: Add support to configure AXI burst size Tanmay Jagdale
` (2 preceding siblings ...)
2021-09-02 16:32 ` [PATCH 0/2] coresight: tmc: Add support to configure AXI " Mike Leach
@ 2021-09-07 17:17 ` Mathieu Poirier
3 siblings, 0 replies; 8+ messages in thread
From: Mathieu Poirier @ 2021-09-07 17:17 UTC (permalink / raw)
To: Tanmay Jagdale
Cc: suzuki.poulose, mike.leach, leo.yan, robh+dt, coresight,
linux-arm-kernel, devicetree, al.grant, sgoutham, lcherian,
bbhushan2
On Wed, Sep 01, 2021 at 06:40:47PM +0530, Tanmay Jagdale wrote:
> Add a new device tree parameter, "arm,max-burst-size" to configure
> the max burst size that can be initiated by TMC-ETR on the AXI bus.
>
> Also add description of this property in coresight documentation.
>
> This patch series applies on top of the coresight next branch [1].
> https://git.kernel.org/pub/scm/linux/kernel/git/coresight/linux.git/log/?h=next
>
> Tanmay Jagdale (2):
> dt-bindings: coresight: Add burst size for TMC
> coresight: tmc: Configure AXI write burst size
>
> .../devicetree/bindings/arm/coresight.txt | 5 +++++
> .../hwtracing/coresight/coresight-tmc-core.c | 21 +++++++++++++++++--
> .../hwtracing/coresight/coresight-tmc-etr.c | 3 ++-
> drivers/hwtracing/coresight/coresight-tmc.h | 6 +++++-
> 4 files changed, 31 insertions(+), 4 deletions(-)
I have applied this set - it will show up in the coresight-next branch on Monday
once 5.15-rc1 has been released.
Thanks,
Mathieu
>
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 8+ messages in thread