* [PATCH AUTOSEL 5.4 21/37] MIPS: mscc: ocelot: disable all switch ports by default
[not found] <20210910002143.175731-1-sashal@kernel.org>
@ 2021-09-10 0:21 ` Sasha Levin
2021-09-10 0:21 ` [PATCH AUTOSEL 5.4 22/37] MIPS: mscc: ocelot: mark the phy-mode for internal PHY ports Sasha Levin
1 sibling, 0 replies; 3+ messages in thread
From: Sasha Levin @ 2021-09-10 0:21 UTC (permalink / raw)
To: linux-kernel, stable
Cc: Vladimir Oltean, Thomas Bogendoerfer, Sasha Levin, linux-mips,
devicetree
From: Vladimir Oltean <vladimir.oltean@nxp.com>
[ Upstream commit 0181f6f19c6c35b24f1516d8db22f3bbce762633 ]
The ocelot switch driver used to ignore ports which do not have a
phy-handle property and not probe those, but this is not quite ok since
it is valid to not have a phy-handle property if there is a fixed-link.
It seems that checking for a phy-handle was a proxy for the proper check
which is for the status, but that doesn't make a lot of sense, since the
ocelot driver already iterates using for_each_available_child_of_node
which skips the disabled ports, so I have no idea.
Anyway, a widespread pattern in device trees is for a SoC dtsi to
disable by default all hardware, and let board dts files enable what is
used. So let's do that and enable only the ports with a phy-handle in
the pcb120 and pcb123 device tree files.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
arch/mips/boot/dts/mscc/ocelot.dtsi | 11 +++++++++++
arch/mips/boot/dts/mscc/ocelot_pcb120.dts | 8 ++++++++
arch/mips/boot/dts/mscc/ocelot_pcb123.dts | 4 ++++
3 files changed, 23 insertions(+)
diff --git a/arch/mips/boot/dts/mscc/ocelot.dtsi b/arch/mips/boot/dts/mscc/ocelot.dtsi
index 797d336db54d..87821b4dfa50 100644
--- a/arch/mips/boot/dts/mscc/ocelot.dtsi
+++ b/arch/mips/boot/dts/mscc/ocelot.dtsi
@@ -148,36 +148,47 @@ ethernet-ports {
port0: port@0 {
reg = <0>;
+ status = "disabled";
};
port1: port@1 {
reg = <1>;
+ status = "disabled";
};
port2: port@2 {
reg = <2>;
+ status = "disabled";
};
port3: port@3 {
reg = <3>;
+ status = "disabled";
};
port4: port@4 {
reg = <4>;
+ status = "disabled";
};
port5: port@5 {
reg = <5>;
+ status = "disabled";
};
port6: port@6 {
reg = <6>;
+ status = "disabled";
};
port7: port@7 {
reg = <7>;
+ status = "disabled";
};
port8: port@8 {
reg = <8>;
+ status = "disabled";
};
port9: port@9 {
reg = <9>;
+ status = "disabled";
};
port10: port@10 {
reg = <10>;
+ status = "disabled";
};
};
};
diff --git a/arch/mips/boot/dts/mscc/ocelot_pcb120.dts b/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
index 33991fd209f5..7da9ed2da248 100644
--- a/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
+++ b/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
@@ -59,40 +59,48 @@ phy4: ethernet-phy@3 {
};
&port0 {
+ status = "okay";
phy-handle = <&phy0>;
};
&port1 {
+ status = "okay";
phy-handle = <&phy1>;
};
&port2 {
+ status = "okay";
phy-handle = <&phy2>;
};
&port3 {
+ status = "okay";
phy-handle = <&phy3>;
};
&port4 {
+ status = "okay";
phy-handle = <&phy7>;
phy-mode = "sgmii";
phys = <&serdes 4 SERDES1G(2)>;
};
&port5 {
+ status = "okay";
phy-handle = <&phy4>;
phy-mode = "sgmii";
phys = <&serdes 5 SERDES1G(5)>;
};
&port6 {
+ status = "okay";
phy-handle = <&phy6>;
phy-mode = "sgmii";
phys = <&serdes 6 SERDES1G(3)>;
};
&port9 {
+ status = "okay";
phy-handle = <&phy5>;
phy-mode = "sgmii";
phys = <&serdes 9 SERDES1G(4)>;
diff --git a/arch/mips/boot/dts/mscc/ocelot_pcb123.dts b/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
index ef852f382da8..7d7e638791dd 100644
--- a/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
+++ b/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
@@ -47,17 +47,21 @@ &mdio0 {
};
&port0 {
+ status = "okay";
phy-handle = <&phy0>;
};
&port1 {
+ status = "okay";
phy-handle = <&phy1>;
};
&port2 {
+ status = "okay";
phy-handle = <&phy2>;
};
&port3 {
+ status = "okay";
phy-handle = <&phy3>;
};
--
2.30.2
^ permalink raw reply related [flat|nested] 3+ messages in thread* [PATCH AUTOSEL 5.4 22/37] MIPS: mscc: ocelot: mark the phy-mode for internal PHY ports
[not found] <20210910002143.175731-1-sashal@kernel.org>
2021-09-10 0:21 ` [PATCH AUTOSEL 5.4 21/37] MIPS: mscc: ocelot: disable all switch ports by default Sasha Levin
@ 2021-09-10 0:21 ` Sasha Levin
2021-09-12 10:14 ` Vladimir Oltean
1 sibling, 1 reply; 3+ messages in thread
From: Sasha Levin @ 2021-09-10 0:21 UTC (permalink / raw)
To: linux-kernel, stable
Cc: Vladimir Oltean, Thomas Bogendoerfer, Sasha Levin, linux-mips,
devicetree
From: Vladimir Oltean <vladimir.oltean@nxp.com>
[ Upstream commit eba54cbb92d28b4f6dc1ed5f73f5187b09d82c08 ]
The ocelot driver was converted to phylink, and that expects a valid
phy_interface_t. Without a phy-mode, of_get_phy_mode returns
PHY_INTERFACE_MODE_NA, which is not ideal because phylink rejects that.
The ocelot driver was patched to treat PHY_INTERFACE_MODE_NA as
PHY_INTERFACE_MODE_INTERNAL to work with the broken DT blobs, but we
should fix the device trees and specify the phy-mode too.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---
arch/mips/boot/dts/mscc/ocelot_pcb120.dts | 4 ++++
arch/mips/boot/dts/mscc/ocelot_pcb123.dts | 4 ++++
2 files changed, 8 insertions(+)
diff --git a/arch/mips/boot/dts/mscc/ocelot_pcb120.dts b/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
index 7da9ed2da248..8555fe3e9517 100644
--- a/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
+++ b/arch/mips/boot/dts/mscc/ocelot_pcb120.dts
@@ -61,21 +61,25 @@ phy4: ethernet-phy@3 {
&port0 {
status = "okay";
phy-handle = <&phy0>;
+ phy-mode = "internal";
};
&port1 {
status = "okay";
phy-handle = <&phy1>;
+ phy-mode = "internal";
};
&port2 {
status = "okay";
phy-handle = <&phy2>;
+ phy-mode = "internal";
};
&port3 {
status = "okay";
phy-handle = <&phy3>;
+ phy-mode = "internal";
};
&port4 {
diff --git a/arch/mips/boot/dts/mscc/ocelot_pcb123.dts b/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
index 7d7e638791dd..0185045c7630 100644
--- a/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
+++ b/arch/mips/boot/dts/mscc/ocelot_pcb123.dts
@@ -49,19 +49,23 @@ &mdio0 {
&port0 {
status = "okay";
phy-handle = <&phy0>;
+ phy-mode = "internal";
};
&port1 {
status = "okay";
phy-handle = <&phy1>;
+ phy-mode = "internal";
};
&port2 {
status = "okay";
phy-handle = <&phy2>;
+ phy-mode = "internal";
};
&port3 {
status = "okay";
phy-handle = <&phy3>;
+ phy-mode = "internal";
};
--
2.30.2
^ permalink raw reply related [flat|nested] 3+ messages in thread