* [PATCH v9, 0/2] soc: mediatek: mmsys: add mt8192 mmsys support @ 2021-09-30 13:59 Yongqiang Niu 2021-09-30 13:59 ` [PATCH v9, 1/2] soc: mediatek: mmsys: add comp OVL_2L2/POSTMASK/RDMA4 Yongqiang Niu 2021-09-30 13:59 ` [PATCH v9, 2/2] soc: mediatek: mmsys: Add mt8192 mmsys routing table Yongqiang Niu 0 siblings, 2 replies; 4+ messages in thread From: Yongqiang Niu @ 2021-09-30 13:59 UTC (permalink / raw) To: Chun-Kuang Hu Cc: Rob Herring, Matthias Brugger, Philipp Zabel, David Airlie, Daniel Vetter, Jassi Brar, Yongqiang Niu, Fabien Parent, Dennis YC Hsieh, devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group, Hsin-Yi Wang base 5.15 Yongqiang Niu (2): soc: mediatek: mmsys: add comp OVL_2L2/POSTMASK/RDMA4 soc: mediatek: mmsys: Add mt8192 mmsys routing table drivers/soc/mediatek/mt8192-mmsys.h | 77 ++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 11 ++++ include/linux/soc/mediatek/mtk-mmsys.h | 3 + 3 files changed, 91 insertions(+) create mode 100644 drivers/soc/mediatek/mt8192-mmsys.h -- 2.25.1 ^ permalink raw reply [flat|nested] 4+ messages in thread
* [PATCH v9, 1/2] soc: mediatek: mmsys: add comp OVL_2L2/POSTMASK/RDMA4 2021-09-30 13:59 [PATCH v9, 0/2] soc: mediatek: mmsys: add mt8192 mmsys support Yongqiang Niu @ 2021-09-30 13:59 ` Yongqiang Niu 2021-09-30 13:59 ` [PATCH v9, 2/2] soc: mediatek: mmsys: Add mt8192 mmsys routing table Yongqiang Niu 1 sibling, 0 replies; 4+ messages in thread From: Yongqiang Niu @ 2021-09-30 13:59 UTC (permalink / raw) To: Chun-Kuang Hu Cc: Rob Herring, Matthias Brugger, Philipp Zabel, David Airlie, Daniel Vetter, Jassi Brar, Yongqiang Niu, Fabien Parent, Dennis YC Hsieh, devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group, Hsin-Yi Wang, Enric Balletbo i Serra This patch add some more ddp component OVL_2L2 is ovl which include 2 layers overlay POSTMASK control round corner for display frame RDMA4 read dma buffer Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- include/linux/soc/mediatek/mtk-mmsys.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h index 2228bf6133da..4bba275e235a 100644 --- a/include/linux/soc/mediatek/mtk-mmsys.h +++ b/include/linux/soc/mediatek/mtk-mmsys.h @@ -29,13 +29,16 @@ enum mtk_ddp_comp_id { DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_OVL_2L1, + DDP_COMPONENT_OVL_2L2, DDP_COMPONENT_OVL1, + DDP_COMPONENT_POSTMASK0, DDP_COMPONENT_PWM0, DDP_COMPONENT_PWM1, DDP_COMPONENT_PWM2, DDP_COMPONENT_RDMA0, DDP_COMPONENT_RDMA1, DDP_COMPONENT_RDMA2, + DDP_COMPONENT_RDMA4, DDP_COMPONENT_UFOE, DDP_COMPONENT_WDMA0, DDP_COMPONENT_WDMA1, -- 2.25.1 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* [PATCH v9, 2/2] soc: mediatek: mmsys: Add mt8192 mmsys routing table 2021-09-30 13:59 [PATCH v9, 0/2] soc: mediatek: mmsys: add mt8192 mmsys support Yongqiang Niu 2021-09-30 13:59 ` [PATCH v9, 1/2] soc: mediatek: mmsys: add comp OVL_2L2/POSTMASK/RDMA4 Yongqiang Niu @ 2021-09-30 13:59 ` Yongqiang Niu 2021-10-01 6:46 ` Enric Balletbo Serra 1 sibling, 1 reply; 4+ messages in thread From: Yongqiang Niu @ 2021-09-30 13:59 UTC (permalink / raw) To: Chun-Kuang Hu Cc: Rob Herring, Matthias Brugger, Philipp Zabel, David Airlie, Daniel Vetter, Jassi Brar, Yongqiang Niu, Fabien Parent, Dennis YC Hsieh, devicetree, linux-arm-kernel, linux-mediatek, linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group, Hsin-Yi Wang, Enric Balletbo i Serra mt8192 has different routing registers than mt8183 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> --- drivers/soc/mediatek/mt8192-mmsys.h | 77 +++++++++++++++++++++++++++++ drivers/soc/mediatek/mtk-mmsys.c | 11 +++++ 2 files changed, 88 insertions(+) create mode 100644 drivers/soc/mediatek/mt8192-mmsys.h diff --git a/drivers/soc/mediatek/mt8192-mmsys.h b/drivers/soc/mediatek/mt8192-mmsys.h new file mode 100644 index 000000000000..7ea1531ee8af --- /dev/null +++ b/drivers/soc/mediatek/mt8192-mmsys.h @@ -0,0 +1,77 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT8192_MMSYS_H +#define __SOC_MEDIATEK_MT8192_MMSYS_H + +#define MT8192_MMSYS_OVL_MOUT_EN 0xf04 +#define MT8192_DISP_OVL1_2L_MOUT_EN 0xf08 +#define MT8192_DISP_OVL0_2L_MOUT_EN 0xf18 +#define MT8192_DISP_OVL0_MOUT_EN 0xf1c +#define MT8192_DISP_RDMA0_SEL_IN 0xf2c +#define MT8192_DISP_RDMA0_SOUT_SEL 0xf30 +#define MT8192_DISP_CCORR0_SOUT_SEL 0xf34 +#define MT8192_DISP_AAL0_SEL_IN 0xf38 +#define MT8192_DISP_DITHER0_MOUT_EN 0xf3c +#define MT8192_DISP_DSI0_SEL_IN 0xf40 +#define MT8192_DISP_OVL2_2L_MOUT_EN 0xf4c + +#define MT8192_DISP_OVL0_GO_BLEND BIT(0) +#define MT8192_DITHER0_MOUT_IN_DSI0 BIT(0) +#define MT8192_OVL0_MOUT_EN_DISP_RDMA0 BIT(0) +#define MT8192_OVL2_2L_MOUT_EN_RDMA4 BIT(0) +#define MT8192_DISP_OVL0_GO_BG BIT(1) +#define MT8192_DISP_OVL0_2L_GO_BLEND BIT(2) +#define MT8192_DISP_OVL0_2L_GO_BG BIT(3) +#define MT8192_OVL1_2L_MOUT_EN_RDMA1 BIT(4) +#define MT8192_OVL0_MOUT_EN_OVL0_2L BIT(4) +#define MT8192_RDMA0_SEL_IN_OVL0_2L 0x3 +#define MT8192_RDMA0_SOUT_COLOR0 0x1 +#define MT8192_CCORR0_SOUT_AAL0 0x1 +#define MT8192_AAL0_SEL_IN_CCORR0 0x1 +#define MT8192_DSI0_SEL_IN_DITHER0 0x1 + +static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = { + { + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, + MT8192_DISP_OVL0_2L_MOUT_EN, MT8192_OVL0_MOUT_EN_DISP_RDMA0, + MT8192_OVL0_MOUT_EN_DISP_RDMA0 + }, { + DDP_COMPONENT_OVL_2L2, DDP_COMPONENT_RDMA4, + MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4, + MT8192_OVL2_2L_MOUT_EN_RDMA4 + }, { + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, + MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0, + MT8192_DITHER0_MOUT_IN_DSI0 + }, { + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, + MT8192_DISP_RDMA0_SEL_IN, MT8192_RDMA0_SEL_IN_OVL0_2L, + MT8192_RDMA0_SEL_IN_OVL0_2L + }, { + DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0, + MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0, + MT8192_AAL0_SEL_IN_CCORR0 + }, { + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, + MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0, + MT8192_DSI0_SEL_IN_DITHER0 + }, { + DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, + MT8192_DISP_RDMA0_SOUT_SEL, MT8192_RDMA0_SOUT_COLOR0, + MT8192_RDMA0_SOUT_COLOR0 + }, { + DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0, + MT8192_DISP_CCORR0_SOUT_SEL, MT8192_CCORR0_SOUT_AAL0, + MT8192_CCORR0_SOUT_AAL0 + }, { + DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0, + MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_GO_BG, + MT8192_DISP_OVL0_GO_BG, + }, { + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, + MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_2L_GO_BLEND, + MT8192_DISP_OVL0_2L_GO_BLEND, + } +}; + +#endif /* __SOC_MEDIATEK_MT8192_MMSYS_H */ diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c index a78e88f27b62..6e97d1468183 100644 --- a/drivers/soc/mediatek/mtk-mmsys.c +++ b/drivers/soc/mediatek/mtk-mmsys.c @@ -14,6 +14,7 @@ #include "mt8167-mmsys.h" #include "mt8183-mmsys.h" #include "mt8365-mmsys.h" +#include "mt8192-mmsys.h" static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { .clk_driver = "clk-mt2701-mm", @@ -59,6 +60,12 @@ static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = { .num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table), }; +static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { + .clk_driver = "clk-mt8192-mm", + .routes = mmsys_mt8192_routing_table, + .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table), +}; + struct mtk_mmsys { void __iomem *regs; const struct mtk_mmsys_driver_data *data; @@ -171,6 +178,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = { .compatible = "mediatek,mt8365-mmsys", .data = &mt8365_mmsys_driver_data, }, + { + .compatible = "mediatek,mt8192-mmsys", + .data = &mt8192_mmsys_driver_data, + }, { } }; -- 2.25.1 ^ permalink raw reply related [flat|nested] 4+ messages in thread
* Re: [PATCH v9, 2/2] soc: mediatek: mmsys: Add mt8192 mmsys routing table 2021-09-30 13:59 ` [PATCH v9, 2/2] soc: mediatek: mmsys: Add mt8192 mmsys routing table Yongqiang Niu @ 2021-10-01 6:46 ` Enric Balletbo Serra 0 siblings, 0 replies; 4+ messages in thread From: Enric Balletbo Serra @ 2021-10-01 6:46 UTC (permalink / raw) To: Yongqiang Niu Cc: Chun-Kuang Hu, Rob Herring, Matthias Brugger, Philipp Zabel, David Airlie, Daniel Vetter, Jassi Brar, Fabien Parent, Dennis YC Hsieh, devicetree, Linux ARM, moderated list:ARM/Mediatek SoC support, linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group, Hsin-Yi Wang, Enric Balletbo i Serra Hi Yongqiang, This patch already have my reviewed tag but I just noticed a small nit Missatge de Yongqiang Niu <yongqiang.niu@mediatek.com> del dia dj., 30 de set. 2021 a les 16:00: > > mt8192 has different routing registers than mt8183 > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > Reviewed-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> > --- > drivers/soc/mediatek/mt8192-mmsys.h | 77 +++++++++++++++++++++++++++++ > drivers/soc/mediatek/mtk-mmsys.c | 11 +++++ > 2 files changed, 88 insertions(+) > create mode 100644 drivers/soc/mediatek/mt8192-mmsys.h > > diff --git a/drivers/soc/mediatek/mt8192-mmsys.h b/drivers/soc/mediatek/mt8192-mmsys.h > new file mode 100644 > index 000000000000..7ea1531ee8af > --- /dev/null > +++ b/drivers/soc/mediatek/mt8192-mmsys.h > @@ -0,0 +1,77 @@ > +/* SPDX-License-Identifier: GPL-2.0-only */ > + > +#ifndef __SOC_MEDIATEK_MT8192_MMSYS_H > +#define __SOC_MEDIATEK_MT8192_MMSYS_H > + > +#define MT8192_MMSYS_OVL_MOUT_EN 0xf04 > +#define MT8192_DISP_OVL1_2L_MOUT_EN 0xf08 > +#define MT8192_DISP_OVL0_2L_MOUT_EN 0xf18 > +#define MT8192_DISP_OVL0_MOUT_EN 0xf1c > +#define MT8192_DISP_RDMA0_SEL_IN 0xf2c > +#define MT8192_DISP_RDMA0_SOUT_SEL 0xf30 > +#define MT8192_DISP_CCORR0_SOUT_SEL 0xf34 > +#define MT8192_DISP_AAL0_SEL_IN 0xf38 > +#define MT8192_DISP_DITHER0_MOUT_EN 0xf3c > +#define MT8192_DISP_DSI0_SEL_IN 0xf40 > +#define MT8192_DISP_OVL2_2L_MOUT_EN 0xf4c > + > +#define MT8192_DISP_OVL0_GO_BLEND BIT(0) > +#define MT8192_DITHER0_MOUT_IN_DSI0 BIT(0) > +#define MT8192_OVL0_MOUT_EN_DISP_RDMA0 BIT(0) > +#define MT8192_OVL2_2L_MOUT_EN_RDMA4 BIT(0) > +#define MT8192_DISP_OVL0_GO_BG BIT(1) > +#define MT8192_DISP_OVL0_2L_GO_BLEND BIT(2) > +#define MT8192_DISP_OVL0_2L_GO_BG BIT(3) > +#define MT8192_OVL1_2L_MOUT_EN_RDMA1 BIT(4) > +#define MT8192_OVL0_MOUT_EN_OVL0_2L BIT(4) > +#define MT8192_RDMA0_SEL_IN_OVL0_2L 0x3 > +#define MT8192_RDMA0_SOUT_COLOR0 0x1 > +#define MT8192_CCORR0_SOUT_AAL0 0x1 > +#define MT8192_AAL0_SEL_IN_CCORR0 0x1 > +#define MT8192_DSI0_SEL_IN_DITHER0 0x1 > + > +static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = { > + { > + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, > + MT8192_DISP_OVL0_2L_MOUT_EN, MT8192_OVL0_MOUT_EN_DISP_RDMA0, > + MT8192_OVL0_MOUT_EN_DISP_RDMA0 > + }, { > + DDP_COMPONENT_OVL_2L2, DDP_COMPONENT_RDMA4, > + MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4, > + MT8192_OVL2_2L_MOUT_EN_RDMA4 > + }, { > + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, > + MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0, > + MT8192_DITHER0_MOUT_IN_DSI0 > + }, { > + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, > + MT8192_DISP_RDMA0_SEL_IN, MT8192_RDMA0_SEL_IN_OVL0_2L, > + MT8192_RDMA0_SEL_IN_OVL0_2L > + }, { > + DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0, > + MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0, > + MT8192_AAL0_SEL_IN_CCORR0 > + }, { > + DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0, > + MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0, > + MT8192_DSI0_SEL_IN_DITHER0 > + }, { > + DDP_COMPONENT_RDMA0, DDP_COMPONENT_COLOR0, > + MT8192_DISP_RDMA0_SOUT_SEL, MT8192_RDMA0_SOUT_COLOR0, > + MT8192_RDMA0_SOUT_COLOR0 > + }, { > + DDP_COMPONENT_CCORR, DDP_COMPONENT_AAL0, > + MT8192_DISP_CCORR0_SOUT_SEL, MT8192_CCORR0_SOUT_AAL0, > + MT8192_CCORR0_SOUT_AAL0 > + }, { > + DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL_2L0, > + MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_GO_BG, > + MT8192_DISP_OVL0_GO_BG, > + }, { > + DDP_COMPONENT_OVL_2L0, DDP_COMPONENT_RDMA0, > + MT8192_MMSYS_OVL_MOUT_EN, MT8192_DISP_OVL0_2L_GO_BLEND, > + MT8192_DISP_OVL0_2L_GO_BLEND, > + } > +}; > + > +#endif /* __SOC_MEDIATEK_MT8192_MMSYS_H */ > diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c > index a78e88f27b62..6e97d1468183 100644 > --- a/drivers/soc/mediatek/mtk-mmsys.c > +++ b/drivers/soc/mediatek/mtk-mmsys.c > @@ -14,6 +14,7 @@ > #include "mt8167-mmsys.h" > #include "mt8183-mmsys.h" > #include "mt8365-mmsys.h" > +#include "mt8192-mmsys.h" > > static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { > .clk_driver = "clk-mt2701-mm", > @@ -59,6 +60,12 @@ static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = { > .num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table), > }; > > +static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = { > + .clk_driver = "clk-mt8192-mm", > + .routes = mmsys_mt8192_routing_table, > + .num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table), > +}; > + For better readability it would be nice if you put this structure by SoC order. That's before mt8365 struct and after mt8183 struct. > struct mtk_mmsys { > void __iomem *regs; > const struct mtk_mmsys_driver_data *data; > @@ -171,6 +178,10 @@ static const struct of_device_id of_match_mtk_mmsys[] = { > .compatible = "mediatek,mt8365-mmsys", > .data = &mt8365_mmsys_driver_data, > }, > + { > + .compatible = "mediatek,mt8192-mmsys", > + .data = &mt8192_mmsys_driver_data, > + }, The same here, for better readability would be nice if you put this fields by SoC order. That's before mt8365 fields and after mt8183 fields. Thanks, Enric > { } > }; > > -- > 2.25.1 > ^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2021-10-01 6:47 UTC | newest] Thread overview: 4+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2021-09-30 13:59 [PATCH v9, 0/2] soc: mediatek: mmsys: add mt8192 mmsys support Yongqiang Niu 2021-09-30 13:59 ` [PATCH v9, 1/2] soc: mediatek: mmsys: add comp OVL_2L2/POSTMASK/RDMA4 Yongqiang Niu 2021-09-30 13:59 ` [PATCH v9, 2/2] soc: mediatek: mmsys: Add mt8192 mmsys routing table Yongqiang Niu 2021-10-01 6:46 ` Enric Balletbo Serra
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