From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5964DC4332F for ; Fri, 8 Oct 2021 15:44:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3F94361027 for ; Fri, 8 Oct 2021 15:44:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243294AbhJHPqH (ORCPT ); Fri, 8 Oct 2021 11:46:07 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36048 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243220AbhJHPpw (ORCPT ); Fri, 8 Oct 2021 11:45:52 -0400 Received: from mail-ed1-x52c.google.com (mail-ed1-x52c.google.com [IPv6:2a00:1450:4864:20::52c]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 504A7C061762 for ; Fri, 8 Oct 2021 08:43:57 -0700 (PDT) Received: by mail-ed1-x52c.google.com with SMTP id d9so14090433edh.5 for ; Fri, 08 Oct 2021 08:43:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=J0QKzYHFcrWp6rGHQjbwElQWpCaDdhPkqu3ZduPHKAU=; b=cdOhmqR6khu1y2lHUV5QBLHq3uWr3E0vo1geqNyGg7+YmMK8at0VppYJdqpsLigdJv /8MT5TKPRDVAarSgs7Ayvbg5oWE/0vRL87moLh2BditqD1nRnNFY/9Xe4GF7y+sv27Rk vplmSIb76doL3Bg97EEOMiPqHsEeu5FxiExg0Ti6MdWRrCqHrCJojrqh0AEUsFRW2XjO HbDbLOtwpep7CIwIJbfKQKg3S8NZ2uajbJOOAsDqn+QxMRfH1XGUdbQ9ggPNHc6zzUZ5 nRffWnxA8PHgr3nHVCtdXvZbrTjDvcVqKQrb565lul+n9/6F0sae7IsqTTK0S2vo0gvY xJ2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=J0QKzYHFcrWp6rGHQjbwElQWpCaDdhPkqu3ZduPHKAU=; b=s+8kwJkFyywPD2Syh+skKoaFEKAkthiO2DGyGAM1OVuGnVUZGPBzqmVedADnkK54Wp x53Rdso6dNmPZjnsHRX0rTVjKQvOrpzUEVYvUycbUG0pE+bxWn3CSS3A1ia3wmpSxJxH WSu5Lf6o8KUKclkwrWbbM3+/WXDjj1xW05DQkumtxC70D/FjsWoXmlmqDttAM7AHTX9X fLjF5sYyJC6zgzx3lNI8XVtFtpABAk5ObbN0ssJPerN8B80V5ZsYEYN+SteEVqtlwh2l vbYMWAQZPtQxogE5NfTRuI5s3t/VWJuDVZEf0rd6C7GLKf3jllHUwPDjYTWnMFUTRIxl SI1g== X-Gm-Message-State: AOAM53210CzpEgKMn0LzRFsecQ8GQmWz8ZM/fM4fnfTRwunBDHxGQDwH gR2SjU2nmRdqasgQ6wa5wpwsMA== X-Google-Smtp-Source: ABdhPJwp556tCNysIjVve7LoIjl+z4ujnWlNA9JzdXsjruUyYiLDcBmIw+X1FtL2xDCW8/dEjCdJfw== X-Received: by 2002:a17:907:75c1:: with SMTP id jl1mr5173678ejc.288.1633707834786; Fri, 08 Oct 2021 08:43:54 -0700 (PDT) Received: from localhost ([31.134.121.151]) by smtp.gmail.com with ESMTPSA id cr9sm1192524edb.17.2021.10.08.08.43.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Oct 2021 08:43:53 -0700 (PDT) From: Sam Protsenko To: Krzysztof Kozlowski , Sylwester Nawrocki , =?UTF-8?q?Pawe=C5=82=20Chmiel?= , Chanwoo Choi , Tomasz Figa , Rob Herring , Stephen Boyd , Michael Turquette Cc: Ryu Euiyoul , Tom Gall , Sumit Semwal , John Stultz , Amit Pundir , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org Subject: [PATCH v3 0/5] clk: samsung: Introduce Exynos850 SoC clock driver Date: Fri, 8 Oct 2021 18:43:47 +0300 Message-Id: <20211008154352.19519-1-semen.protsenko@linaro.org> X-Mailer: git-send-email 2.30.2 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org This patch series provides the implementation for Exynos850 clock driver, its documentation and corresponding changes for Samsung clock infrastructure (adds new PLL types used in Exynos850 SoC, following TRM). I tried to follow already established design for Samsung clock drivers (getting most insights from Exynos5433 clock driver), and integrate the driver into existing infrastructure. The whole driver was implemented from scratch, using mostly TRM and downstream kernel for clock dependencies/hierarchy info. For now only basic clocks are implemented, including next blocks: - CMU_TOP - CMU_PERI - CMU_CORE - CMU_HSI - CMU_DPU Some CMUs are still not implemented, but that can be added in future, when the need arises. The driver also lacks CLKOUT support, PM ops and automatic clocks control (using Q-Channel protocol). All that can be added independently later. Implemented clock tree was tested via UART and MMC drivers, and using DebugFS clk support (e.g. using 'clk_summary' file). In order to keep all clocks running I added 'clk_ignore_unused' kernel param in my local tree, and defined CLOCK_ALLOW_WRITE_DEBUGFS in clk.c for actually testing the clocks via DebugFS. Changes in v3: - Changed the licence for bindings header to GPL+BSD - Added R-b tag by Krzysztof Kozlowski to patches 4/5 and 5/5 Changes in v2: - Added CMU_DPU implementation - Moved bus clock enablement to clk-exynos850.c - See also "v2 changes" list in each particular patch Sam Protsenko (5): clk: samsung: clk-pll: Implement pll0822x PLL type clk: samsung: clk-pll: Implement pll0831x PLL type dt-bindings: clock: Add bindings definitions for Exynos850 CMU dt-bindings: clock: Document Exynos850 CMU bindings clk: samsung: Introduce Exynos850 clock driver .../clock/samsung,exynos850-clock.yaml | 185 ++++ drivers/clk/samsung/Makefile | 1 + drivers/clk/samsung/clk-exynos850.c | 835 ++++++++++++++++++ drivers/clk/samsung/clk-pll.c | 196 ++++ drivers/clk/samsung/clk-pll.h | 2 + include/dt-bindings/clock/exynos850.h | 141 +++ 6 files changed, 1360 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/samsung,exynos850-clock.yaml create mode 100644 drivers/clk/samsung/clk-exynos850.c create mode 100644 include/dt-bindings/clock/exynos850.h -- 2.30.2