From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D8670C4321E for ; Mon, 18 Oct 2021 13:32:03 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id C53D661373 for ; Mon, 18 Oct 2021 13:32:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232865AbhJRNeM (ORCPT ); Mon, 18 Oct 2021 09:34:12 -0400 Received: from foss.arm.com ([217.140.110.172]:37618 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232633AbhJRNcZ (ORCPT ); Mon, 18 Oct 2021 09:32:25 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 967F8113E; Mon, 18 Oct 2021 06:30:13 -0700 (PDT) Received: from bogus (unknown [10.57.25.56]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 1A02F3F73D; Mon, 18 Oct 2021 06:30:06 -0700 (PDT) Date: Mon, 18 Oct 2021 14:30:04 +0100 From: Sudeep Holla To: Rob Herring Cc: Russell King , James Morse , Catalin Marinas , Sudeep Holla , Will Deacon , Guo Ren , Jonas Bonn , Stefan Kristiansson , Stafford Horne , Michael Ellerman , Paul Walmsley , Palmer Dabbelt , Albert Ou , Yoshinori Sato , Rich Felker , x86@kernel.org, Greg Kroah-Hartman , Florian Fainelli , Ray Jui , Scott Branden , bcm-kernel-feedback-list@broadcom.com, Benjamin Herrenschmidt , Paul Mackerras , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , "Rafael J. Wysocki" , Frank Rowand , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-csky@vger.kernel.org, openrisc@lists.librecores.org, linuxppc-dev@lists.ozlabs.org, linux-riscv@lists.infradead.org, linux-sh@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH 11/12] cacheinfo: Allow for >32-bit cache 'id' Message-ID: <20211018133004.7pcbfdsvrjgjitpj@bogus> References: <20211006164332.1981454-1-robh@kernel.org> <20211006164332.1981454-12-robh@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20211006164332.1981454-12-robh@kernel.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed, Oct 06, 2021 at 11:43:31AM -0500, Rob Herring wrote: > In preparation to set the cache 'id' based on the CPU h/w ids, allow for > 64-bit bit 'id' value. The only case that needs this is arm64, so > unsigned long is sufficient. > Reviewed-by: Sudeep Holla -- Regards, Sudeep