[PATCH v1 2/3] arm64: dts: renesas: r8a77951: Add CR7 realtime processor

[Julien Massot <julien.massot@iot.bzh>]

r8a77951 as some other members of rcar gen3 soc series
has a Cortex R7 processor.
This processor shares the same mapped devices and memory mapping.

Choose 0x40040000 area to store the Cortex-R7 firmware.

Signed-off-by: Julien Massot <julien.massot@iot.bzh>
---

No change since RFC, Geert most likely it sounds better
to drop this patch in v2 ?

---
 arch/arm64/boot/dts/renesas/r8a77951-ulcb.dts | 15 +++++++++++++++
 arch/arm64/boot/dts/renesas/r8a77951.dtsi     |  7 +++++++
 2 files changed, 22 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a77951-ulcb.dts b/arch/arm64/boot/dts/renesas/r8a77951-ulcb.dts
index 06d4e948eb0f..703d0d33efe6 100644
--- a/arch/arm64/boot/dts/renesas/r8a77951-ulcb.dts
+++ b/arch/arm64/boot/dts/renesas/r8a77951-ulcb.dts
@@ -34,6 +34,16 @@ memory@700000000 {
 		device_type = "memory";
 		reg = <0x7 0x00000000 0x0 0x40000000>;
 	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		cr7_ram: cr7_ram@40040000 {
+			no-map;
+			reg = <0x0 0x40040000 0x0 0x1fc0000>;
+		};
+	};
 };
 
 &du {
@@ -48,3 +58,8 @@ &du {
 	clock-names = "du.0", "du.1", "du.2", "du.3",
 		      "dclkin.0", "dclkin.1", "dclkin.2", "dclkin.3";
 };
+
+&cr7_rproc {
+	memory-region = <&cr7_ram>;
+	status = "okay";
+};
diff --git a/arch/arm64/boot/dts/renesas/r8a77951.dtsi b/arch/arm64/boot/dts/renesas/r8a77951.dtsi
index 1768a3e6bb8d..3ee247fc5aec 100644
--- a/arch/arm64/boot/dts/renesas/r8a77951.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a77951.dtsi
@@ -366,6 +366,13 @@ soc: soc {
 		#size-cells = <2>;
 		ranges;
 
+		cr7_rproc: cr7 {
+			compatible = "renesas,rcar-cr7";
+			power-domains = <&sysc R8A7795_PD_CR7>;
+			resets = <&cpg 222>;
+			status = "disabled";
+		};
+
 		rwdt: watchdog@e6020000 {
 			compatible = "renesas,r8a7795-wdt", "renesas,rcar-gen3-wdt";
 			reg = <0 0xe6020000 0 0x0c>;
-- 
2.31.1