* [PATCH] ARM: dts: bcm2711: Fix PCIe interrupts
@ 2021-10-29 21:09 Florian Fainelli
2021-11-15 17:32 ` Florian Fainelli
0 siblings, 1 reply; 2+ messages in thread
From: Florian Fainelli @ 2021-10-29 21:09 UTC (permalink / raw)
To: linux-arm-kernel
Cc: Florian Fainelli, Jim Quinlan, Rob Herring,
Nicolas Saenz Julienne,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
open list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
open list
The PCIe host bridge has two interrupt lines, one that goes towards it
PCIE_INTR2 second level interrupt controller and one for its MSI second
level interrupt controller. The first interrupt line is not currently
managed by the driver, which is why it was not a functional problem.
The interrupt-map property was also only listing the PCI_INTA interrupts
when there are also the INTB, C and D.
Reported-by: Jim Quinlan <jim2101024@gmail.com>
Fixes: d5c8dc0d4c88 ("ARM: dts: bcm2711: Enable PCIe controller")
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
---
arch/arm/boot/dts/bcm2711.dtsi | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/bcm2711.dtsi b/arch/arm/boot/dts/bcm2711.dtsi
index 3b60297af7f6..9e01dbca4a01 100644
--- a/arch/arm/boot/dts/bcm2711.dtsi
+++ b/arch/arm/boot/dts/bcm2711.dtsi
@@ -506,11 +506,17 @@ pcie0: pcie@7d500000 {
#address-cells = <3>;
#interrupt-cells = <1>;
#size-cells = <2>;
- interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "pcie", "msi";
interrupt-map-mask = <0x0 0x0 0x0 0x7>;
interrupt-map = <0 0 0 1 &gicv2 GIC_SPI 143
+ IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 2 &gicv2 GIC_SPI 144
+ IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 3 &gicv2 GIC_SPI 145
+ IRQ_TYPE_LEVEL_HIGH>,
+ <0 0 0 4 &gicv2 GIC_SPI 146
IRQ_TYPE_LEVEL_HIGH>;
msi-controller;
msi-parent = <&pcie0>;
--
2.25.1
^ permalink raw reply related [flat|nested] 2+ messages in thread* Re: [PATCH] ARM: dts: bcm2711: Fix PCIe interrupts
2021-10-29 21:09 [PATCH] ARM: dts: bcm2711: Fix PCIe interrupts Florian Fainelli
@ 2021-11-15 17:32 ` Florian Fainelli
0 siblings, 0 replies; 2+ messages in thread
From: Florian Fainelli @ 2021-11-15 17:32 UTC (permalink / raw)
To: bcm-kernel-feedback-list, linux-arm-kernel
Cc: Jim Quinlan, Rob Herring, Nicolas Saenz Julienne,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
moderated list:BROADCOM BCM2711/BCM2835 ARM ARCHITECTURE,
open list
On Fri, 29 Oct 2021 14:09:26 -0700, Florian Fainelli <f.fainelli@gmail.com> wrote:
> The PCIe host bridge has two interrupt lines, one that goes towards it
> PCIE_INTR2 second level interrupt controller and one for its MSI second
> level interrupt controller. The first interrupt line is not currently
> managed by the driver, which is why it was not a functional problem.
>
> The interrupt-map property was also only listing the PCI_INTA interrupts
> when there are also the INTB, C and D.
>
> Reported-by: Jim Quinlan <jim2101024@gmail.com>
> Fixes: d5c8dc0d4c88 ("ARM: dts: bcm2711: Enable PCIe controller")
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
> ---
Applied to https://github.com/Broadcom/stblinux/commits/devicetree/fixes, thanks!
--
Florian
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