* [PATCH 1/9] riscv: dts: canaan: Fix SPI FLASH node names
2021-11-25 15:31 [PATCH 0/9] riscv: dts: Miscellaneous fixes Geert Uytterhoeven
@ 2021-11-25 15:31 ` Geert Uytterhoeven
2021-11-26 4:41 ` Damien Le Moal
2021-11-26 9:54 ` Krzysztof Kozlowski
2021-11-25 15:31 ` [PATCH 2/9] riscv: dts: canaan: Group tuples in interrupt properties Geert Uytterhoeven
` (7 subsequent siblings)
8 siblings, 2 replies; 32+ messages in thread
From: Geert Uytterhoeven @ 2021-11-25 15:31 UTC (permalink / raw)
To: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Damien Le Moal, Lewis Hanly, Krzysztof Kozlowski, Conor Dooley
Cc: devicetree, linux-riscv, Geert Uytterhoeven
"make dtbs_check":
arch/riscv/boot/dts/canaan/sipeed_maix_bit.dt.yaml: spi-flash@0: $nodename:0: 'spi-flash@0' does not match '^flash(@.*)?$'
From schema: Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
Fix this by renaming all SPI FLASH nodes to "flash".
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
---
arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts | 2 +-
arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts | 2 +-
arch/riscv/boot/dts/canaan/sipeed_maix_go.dts | 2 +-
arch/riscv/boot/dts/canaan/sipeed_maixduino.dts | 2 +-
4 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts
index 0bcaf35045e795ed..984872f3d3a9b9ea 100644
--- a/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts
+++ b/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts
@@ -199,7 +199,7 @@ slot@0 {
};
&spi3 {
- spi-flash@0 {
+ flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts
index ac8a03f5867adbd0..7ba99b4da304218e 100644
--- a/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts
+++ b/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts
@@ -201,7 +201,7 @@ slot@0 {
};
&spi3 {
- spi-flash@0 {
+ flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts
index 623998194bc18aab..be9b12c9b374acb3 100644
--- a/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts
+++ b/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts
@@ -209,7 +209,7 @@ slot@0 {
};
&spi3 {
- spi-flash@0 {
+ flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
diff --git a/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts b/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts
index cf605ba0d67e43cd..031c0c28f8195777 100644
--- a/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts
+++ b/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts
@@ -174,7 +174,7 @@ slot@0 {
};
&spi3 {
- spi-flash@0 {
+ flash@0 {
compatible = "jedec,spi-nor";
reg = <0>;
spi-max-frequency = <50000000>;
--
2.25.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH 1/9] riscv: dts: canaan: Fix SPI FLASH node names
2021-11-25 15:31 ` [PATCH 1/9] riscv: dts: canaan: Fix SPI FLASH node names Geert Uytterhoeven
@ 2021-11-26 4:41 ` Damien Le Moal
2021-11-26 9:54 ` Krzysztof Kozlowski
1 sibling, 0 replies; 32+ messages in thread
From: Damien Le Moal @ 2021-11-26 4:41 UTC (permalink / raw)
To: Geert Uytterhoeven, Rob Herring, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Lewis Hanly, Krzysztof Kozlowski, Conor Dooley
Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org
On 2021/11/26 0:31, Geert Uytterhoeven wrote:
> "make dtbs_check":
>
> arch/riscv/boot/dts/canaan/sipeed_maix_bit.dt.yaml: spi-flash@0: $nodename:0: 'spi-flash@0' does not match '^flash(@.*)?$'
> From schema: Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
>
> Fix this by renaming all SPI FLASH nodes to "flash".
>
> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
> ---
> arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts | 2 +-
> arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts | 2 +-
> arch/riscv/boot/dts/canaan/sipeed_maix_go.dts | 2 +-
> arch/riscv/boot/dts/canaan/sipeed_maixduino.dts | 2 +-
> 4 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts
> index 0bcaf35045e795ed..984872f3d3a9b9ea 100644
> --- a/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts
> +++ b/arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts
> @@ -199,7 +199,7 @@ slot@0 {
> };
>
> &spi3 {
> - spi-flash@0 {
> + flash@0 {
> compatible = "jedec,spi-nor";
> reg = <0>;
> spi-max-frequency = <50000000>;
> diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts
> index ac8a03f5867adbd0..7ba99b4da304218e 100644
> --- a/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts
> +++ b/arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts
> @@ -201,7 +201,7 @@ slot@0 {
> };
>
> &spi3 {
> - spi-flash@0 {
> + flash@0 {
> compatible = "jedec,spi-nor";
> reg = <0>;
> spi-max-frequency = <50000000>;
> diff --git a/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts b/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts
> index 623998194bc18aab..be9b12c9b374acb3 100644
> --- a/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts
> +++ b/arch/riscv/boot/dts/canaan/sipeed_maix_go.dts
> @@ -209,7 +209,7 @@ slot@0 {
> };
>
> &spi3 {
> - spi-flash@0 {
> + flash@0 {
> compatible = "jedec,spi-nor";
> reg = <0>;
> spi-max-frequency = <50000000>;
> diff --git a/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts b/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts
> index cf605ba0d67e43cd..031c0c28f8195777 100644
> --- a/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts
> +++ b/arch/riscv/boot/dts/canaan/sipeed_maixduino.dts
> @@ -174,7 +174,7 @@ slot@0 {
> };
>
> &spi3 {
> - spi-flash@0 {
> + flash@0 {
> compatible = "jedec,spi-nor";
> reg = <0>;
> spi-max-frequency = <50000000>;
>
Reviewed-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Tested-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
--
Damien Le Moal
Western Digital Research
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH 1/9] riscv: dts: canaan: Fix SPI FLASH node names
2021-11-25 15:31 ` [PATCH 1/9] riscv: dts: canaan: Fix SPI FLASH node names Geert Uytterhoeven
2021-11-26 4:41 ` Damien Le Moal
@ 2021-11-26 9:54 ` Krzysztof Kozlowski
1 sibling, 0 replies; 32+ messages in thread
From: Krzysztof Kozlowski @ 2021-11-26 9:54 UTC (permalink / raw)
To: Geert Uytterhoeven, Rob Herring, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Damien Le Moal, Lewis Hanly, Conor Dooley
Cc: devicetree, linux-riscv
On 25/11/2021 16:31, Geert Uytterhoeven wrote:
> "make dtbs_check":
>
> arch/riscv/boot/dts/canaan/sipeed_maix_bit.dt.yaml: spi-flash@0: $nodename:0: 'spi-flash@0' does not match '^flash(@.*)?$'
> From schema: Documentation/devicetree/bindings/mtd/jedec,spi-nor.yaml
>
> Fix this by renaming all SPI FLASH nodes to "flash".
>
> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
> ---
> arch/riscv/boot/dts/canaan/sipeed_maix_bit.dts | 2 +-
> arch/riscv/boot/dts/canaan/sipeed_maix_dock.dts | 2 +-
> arch/riscv/boot/dts/canaan/sipeed_maix_go.dts | 2 +-
> arch/riscv/boot/dts/canaan/sipeed_maixduino.dts | 2 +-
> 4 files changed, 4 insertions(+), 4 deletions(-)
>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 2/9] riscv: dts: canaan: Group tuples in interrupt properties
2021-11-25 15:31 [PATCH 0/9] riscv: dts: Miscellaneous fixes Geert Uytterhoeven
2021-11-25 15:31 ` [PATCH 1/9] riscv: dts: canaan: Fix SPI FLASH node names Geert Uytterhoeven
@ 2021-11-25 15:31 ` Geert Uytterhoeven
2021-11-26 4:42 ` Damien Le Moal
2021-11-26 9:53 ` Krzysztof Kozlowski
2021-11-25 15:31 ` [PATCH 3/9] riscv: dts: microchip: mpfs: Drop empty chosen node Geert Uytterhoeven
` (6 subsequent siblings)
8 siblings, 2 replies; 32+ messages in thread
From: Geert Uytterhoeven @ 2021-11-25 15:31 UTC (permalink / raw)
To: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Damien Le Moal, Lewis Hanly, Krzysztof Kozlowski, Conor Dooley
Cc: devicetree, linux-riscv, Geert Uytterhoeven
To improve human readability and enable automatic validation, the tuples
in the various properties containing interrupt specifiers should be
grouped.
Fix this by grouping the tuples of "interrupts" and
"interrupts-extended" properties using angle brackets.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
---
arch/riscv/boot/dts/canaan/k210.dtsi | 23 ++++++++++++-----------
1 file changed, 12 insertions(+), 11 deletions(-)
diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
index 5e8ca8142482153b..56f57118c633b91a 100644
--- a/arch/riscv/boot/dts/canaan/k210.dtsi
+++ b/arch/riscv/boot/dts/canaan/k210.dtsi
@@ -103,8 +103,8 @@ rom0: nvmem@1000 {
clint0: timer@2000000 {
compatible = "canaan,k210-clint", "sifive,clint0";
reg = <0x2000000 0xC000>;
- interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
- &cpu1_intc 3 &cpu1_intc 7>;
+ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+ <&cpu1_intc 3>, <&cpu1_intc 7>;
};
plic0: interrupt-controller@c000000 {
@@ -113,7 +113,7 @@ plic0: interrupt-controller@c000000 {
compatible = "canaan,k210-plic", "sifive,plic-1.0.0";
reg = <0xC000000 0x4000000>;
interrupt-controller;
- interrupts-extended = <&cpu0_intc 11 &cpu1_intc 11>;
+ interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>;
riscv,ndev = <65>;
};
@@ -130,10 +130,11 @@ gpio0: gpio-controller@38001000 {
compatible = "canaan,k210-gpiohs", "sifive,gpio0";
reg = <0x38001000 0x1000>;
interrupt-controller;
- interrupts = <34 35 36 37 38 39 40 41
- 42 43 44 45 46 47 48 49
- 50 51 52 53 54 55 56 57
- 58 59 60 61 62 63 64 65>;
+ interrupts = <34>, <35>, <36>, <37>, <38>, <39>, <40>,
+ <41>, <42>, <43>, <44>, <45>, <46>, <47>,
+ <48>, <49>, <50>, <51>, <52>, <53>, <54>,
+ <55>, <56>, <57>, <58>, <59>, <60>, <61>,
+ <62>, <63>, <64>, <65>;
gpio-controller;
ngpios = <32>;
};
@@ -141,7 +142,7 @@ gpio0: gpio-controller@38001000 {
dmac0: dma-controller@50000000 {
compatible = "snps,axi-dma-1.01a";
reg = <0x50000000 0x1000>;
- interrupts = <27 28 29 30 31 32>;
+ interrupts = <27>, <28>, <29>, <30>, <31>, <32>;
#dma-cells = <1>;
clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>;
clock-names = "core-clk", "cfgr-clk";
@@ -316,7 +317,7 @@ fpioa: pinmux@502b0000 {
timer0: timer@502d0000 {
compatible = "snps,dw-apb-timer";
reg = <0x502D0000 0x100>;
- interrupts = <14 15>;
+ interrupts = <14>, <15>;
clocks = <&sysclk K210_CLK_TIMER0>,
<&sysclk K210_CLK_APB0>;
clock-names = "timer", "pclk";
@@ -326,7 +327,7 @@ timer0: timer@502d0000 {
timer1: timer@502e0000 {
compatible = "snps,dw-apb-timer";
reg = <0x502E0000 0x100>;
- interrupts = <16 17>;
+ interrupts = <16>, <17>;
clocks = <&sysclk K210_CLK_TIMER1>,
<&sysclk K210_CLK_APB0>;
clock-names = "timer", "pclk";
@@ -336,7 +337,7 @@ timer1: timer@502e0000 {
timer2: timer@502f0000 {
compatible = "snps,dw-apb-timer";
reg = <0x502F0000 0x100>;
- interrupts = <18 19>;
+ interrupts = <18>, <19>;
clocks = <&sysclk K210_CLK_TIMER2>,
<&sysclk K210_CLK_APB0>;
clock-names = "timer", "pclk";
--
2.25.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH 2/9] riscv: dts: canaan: Group tuples in interrupt properties
2021-11-25 15:31 ` [PATCH 2/9] riscv: dts: canaan: Group tuples in interrupt properties Geert Uytterhoeven
@ 2021-11-26 4:42 ` Damien Le Moal
2021-11-26 9:53 ` Krzysztof Kozlowski
1 sibling, 0 replies; 32+ messages in thread
From: Damien Le Moal @ 2021-11-26 4:42 UTC (permalink / raw)
To: Geert Uytterhoeven, Rob Herring, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Lewis Hanly, Krzysztof Kozlowski, Conor Dooley
Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org
On 2021/11/26 0:31, Geert Uytterhoeven wrote:
> To improve human readability and enable automatic validation, the tuples
> in the various properties containing interrupt specifiers should be
> grouped.
>
> Fix this by grouping the tuples of "interrupts" and
> "interrupts-extended" properties using angle brackets.
>
> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
> ---
> arch/riscv/boot/dts/canaan/k210.dtsi | 23 ++++++++++++-----------
> 1 file changed, 12 insertions(+), 11 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/canaan/k210.dtsi b/arch/riscv/boot/dts/canaan/k210.dtsi
> index 5e8ca8142482153b..56f57118c633b91a 100644
> --- a/arch/riscv/boot/dts/canaan/k210.dtsi
> +++ b/arch/riscv/boot/dts/canaan/k210.dtsi
> @@ -103,8 +103,8 @@ rom0: nvmem@1000 {
> clint0: timer@2000000 {
> compatible = "canaan,k210-clint", "sifive,clint0";
> reg = <0x2000000 0xC000>;
> - interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
> - &cpu1_intc 3 &cpu1_intc 7>;
> + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
> + <&cpu1_intc 3>, <&cpu1_intc 7>;
> };
>
> plic0: interrupt-controller@c000000 {
> @@ -113,7 +113,7 @@ plic0: interrupt-controller@c000000 {
> compatible = "canaan,k210-plic", "sifive,plic-1.0.0";
> reg = <0xC000000 0x4000000>;
> interrupt-controller;
> - interrupts-extended = <&cpu0_intc 11 &cpu1_intc 11>;
> + interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>;
> riscv,ndev = <65>;
> };
>
> @@ -130,10 +130,11 @@ gpio0: gpio-controller@38001000 {
> compatible = "canaan,k210-gpiohs", "sifive,gpio0";
> reg = <0x38001000 0x1000>;
> interrupt-controller;
> - interrupts = <34 35 36 37 38 39 40 41
> - 42 43 44 45 46 47 48 49
> - 50 51 52 53 54 55 56 57
> - 58 59 60 61 62 63 64 65>;
> + interrupts = <34>, <35>, <36>, <37>, <38>, <39>, <40>,
> + <41>, <42>, <43>, <44>, <45>, <46>, <47>,
> + <48>, <49>, <50>, <51>, <52>, <53>, <54>,
> + <55>, <56>, <57>, <58>, <59>, <60>, <61>,
> + <62>, <63>, <64>, <65>;
> gpio-controller;
> ngpios = <32>;
> };
> @@ -141,7 +142,7 @@ gpio0: gpio-controller@38001000 {
> dmac0: dma-controller@50000000 {
> compatible = "snps,axi-dma-1.01a";
> reg = <0x50000000 0x1000>;
> - interrupts = <27 28 29 30 31 32>;
> + interrupts = <27>, <28>, <29>, <30>, <31>, <32>;
> #dma-cells = <1>;
> clocks = <&sysclk K210_CLK_DMA>, <&sysclk K210_CLK_DMA>;
> clock-names = "core-clk", "cfgr-clk";
> @@ -316,7 +317,7 @@ fpioa: pinmux@502b0000 {
> timer0: timer@502d0000 {
> compatible = "snps,dw-apb-timer";
> reg = <0x502D0000 0x100>;
> - interrupts = <14 15>;
> + interrupts = <14>, <15>;
> clocks = <&sysclk K210_CLK_TIMER0>,
> <&sysclk K210_CLK_APB0>;
> clock-names = "timer", "pclk";
> @@ -326,7 +327,7 @@ timer0: timer@502d0000 {
> timer1: timer@502e0000 {
> compatible = "snps,dw-apb-timer";
> reg = <0x502E0000 0x100>;
> - interrupts = <16 17>;
> + interrupts = <16>, <17>;
> clocks = <&sysclk K210_CLK_TIMER1>,
> <&sysclk K210_CLK_APB0>;
> clock-names = "timer", "pclk";
> @@ -336,7 +337,7 @@ timer1: timer@502e0000 {
> timer2: timer@502f0000 {
> compatible = "snps,dw-apb-timer";
> reg = <0x502F0000 0x100>;
> - interrupts = <18 19>;
> + interrupts = <18>, <19>;
> clocks = <&sysclk K210_CLK_TIMER2>,
> <&sysclk K210_CLK_APB0>;
> clock-names = "timer", "pclk";
>
Reviewed-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
Tested-by: Damien Le Moal <damien.lemoal@opensource.wdc.com>
--
Damien Le Moal
Western Digital Research
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH 2/9] riscv: dts: canaan: Group tuples in interrupt properties
2021-11-25 15:31 ` [PATCH 2/9] riscv: dts: canaan: Group tuples in interrupt properties Geert Uytterhoeven
2021-11-26 4:42 ` Damien Le Moal
@ 2021-11-26 9:53 ` Krzysztof Kozlowski
1 sibling, 0 replies; 32+ messages in thread
From: Krzysztof Kozlowski @ 2021-11-26 9:53 UTC (permalink / raw)
To: Geert Uytterhoeven, Rob Herring, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Damien Le Moal, Lewis Hanly, Conor Dooley
Cc: devicetree, linux-riscv
On 25/11/2021 16:31, Geert Uytterhoeven wrote:
> To improve human readability and enable automatic validation, the tuples
> in the various properties containing interrupt specifiers should be
> grouped.
>
> Fix this by grouping the tuples of "interrupts" and
> "interrupts-extended" properties using angle brackets.
>
> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
> ---
> arch/riscv/boot/dts/canaan/k210.dtsi | 23 ++++++++++++-----------
> 1 file changed, 12 insertions(+), 11 deletions(-)
>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 3/9] riscv: dts: microchip: mpfs: Drop empty chosen node
2021-11-25 15:31 [PATCH 0/9] riscv: dts: Miscellaneous fixes Geert Uytterhoeven
2021-11-25 15:31 ` [PATCH 1/9] riscv: dts: canaan: Fix SPI FLASH node names Geert Uytterhoeven
2021-11-25 15:31 ` [PATCH 2/9] riscv: dts: canaan: Group tuples in interrupt properties Geert Uytterhoeven
@ 2021-11-25 15:31 ` Geert Uytterhoeven
2021-11-26 9:53 ` Krzysztof Kozlowski
2021-11-26 11:45 ` Conor.Dooley
2021-11-25 15:31 ` [PATCH 4/9] riscv: dts: microchip: Group tuples in interrupt properties Geert Uytterhoeven
` (5 subsequent siblings)
8 siblings, 2 replies; 32+ messages in thread
From: Geert Uytterhoeven @ 2021-11-25 15:31 UTC (permalink / raw)
To: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Damien Le Moal, Lewis Hanly, Krzysztof Kozlowski, Conor Dooley
Cc: devicetree, linux-riscv, Geert Uytterhoeven
It does not make sense to have an (empty) chosen node in an SoC-specific
.dtsi, as chosen is meant for system-specific configuration.
It is already provided in microchip-mpfs-icicle-kit.dts anyway.
Fixes: 0fa6107eca4186ad ("RISC-V: Initial DTS for Microchip ICICLE board")
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
---
arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 3 ---
1 file changed, 3 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index c9f6d205d2ba1a5e..794da883acb19256 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -9,9 +9,6 @@ / {
model = "Microchip PolarFire SoC";
compatible = "microchip,mpfs";
- chosen {
- };
-
cpus {
#address-cells = <1>;
#size-cells = <0>;
--
2.25.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH 3/9] riscv: dts: microchip: mpfs: Drop empty chosen node
2021-11-25 15:31 ` [PATCH 3/9] riscv: dts: microchip: mpfs: Drop empty chosen node Geert Uytterhoeven
@ 2021-11-26 9:53 ` Krzysztof Kozlowski
2021-11-26 9:57 ` Geert Uytterhoeven
2021-11-26 11:45 ` Conor.Dooley
1 sibling, 1 reply; 32+ messages in thread
From: Krzysztof Kozlowski @ 2021-11-26 9:53 UTC (permalink / raw)
To: Geert Uytterhoeven, Rob Herring, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Damien Le Moal, Lewis Hanly, Conor Dooley
Cc: devicetree, linux-riscv
On 25/11/2021 16:31, Geert Uytterhoeven wrote:
> It does not make sense to have an (empty) chosen node in an SoC-specific
> .dtsi, as chosen is meant for system-specific configuration.
> It is already provided in microchip-mpfs-icicle-kit.dts anyway.
>
> Fixes: 0fa6107eca4186ad ("RISC-V: Initial DTS for Microchip ICICLE board")
> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
> ---
> arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 3 ---
> 1 file changed, 3 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> index c9f6d205d2ba1a5e..794da883acb19256 100644
> --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> @@ -9,9 +9,6 @@ / {
> model = "Microchip PolarFire SoC";
> compatible = "microchip,mpfs";
>
> - chosen {
> - };
> -
> cpus {
> #address-cells = <1>;
> #size-cells = <0>;
>
Maybe bootloader expects it? E.g. it looks for node and fills it and
would fail if the node is missing?
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH 3/9] riscv: dts: microchip: mpfs: Drop empty chosen node
2021-11-26 9:53 ` Krzysztof Kozlowski
@ 2021-11-26 9:57 ` Geert Uytterhoeven
0 siblings, 0 replies; 32+ messages in thread
From: Geert Uytterhoeven @ 2021-11-26 9:57 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Damien Le Moal, Lewis Hanly, Conor Dooley,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv
Hi Krzysztof,
On Fri, Nov 26, 2021 at 10:53 AM Krzysztof Kozlowski
<krzysztof.kozlowski@canonical.com> wrote:
> On 25/11/2021 16:31, Geert Uytterhoeven wrote:
> > It does not make sense to have an (empty) chosen node in an SoC-specific
> > .dtsi, as chosen is meant for system-specific configuration.
> > It is already provided in microchip-mpfs-icicle-kit.dts anyway.
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^
> >
> > Fixes: 0fa6107eca4186ad ("RISC-V: Initial DTS for Microchip ICICLE board")
> > Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
> > ---
> > arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 3 ---
> > 1 file changed, 3 deletions(-)
> >
> > diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> > index c9f6d205d2ba1a5e..794da883acb19256 100644
> > --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> > +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> > @@ -9,9 +9,6 @@ / {
> > model = "Microchip PolarFire SoC";
> > compatible = "microchip,mpfs";
> >
> > - chosen {
> > - };
> > -
> > cpus {
> > #address-cells = <1>;
> > #size-cells = <0>;
> >
>
> Maybe bootloader expects it? E.g. it looks for node and fills it and
> would fail if the node is missing?
Already present in board DTS.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 3/9] riscv: dts: microchip: mpfs: Drop empty chosen node
2021-11-25 15:31 ` [PATCH 3/9] riscv: dts: microchip: mpfs: Drop empty chosen node Geert Uytterhoeven
2021-11-26 9:53 ` Krzysztof Kozlowski
@ 2021-11-26 11:45 ` Conor.Dooley
1 sibling, 0 replies; 32+ messages in thread
From: Conor.Dooley @ 2021-11-26 11:45 UTC (permalink / raw)
To: geert, robh+dt, paul.walmsley, palmer, aou, damien.lemoal,
Lewis.Hanly, krzysztof.kozlowski
Cc: devicetree, linux-riscv
On 25/11/2021 15:31, Geert Uytterhoeven wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> It does not make sense to have an (empty) chosen node in an SoC-specific
> .dtsi, as chosen is meant for system-specific configuration.
> It is already provided in microchip-mpfs-icicle-kit.dts anyway.
>
> Fixes: 0fa6107eca4186ad ("RISC-V: Initial DTS for Microchip ICICLE board")
> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
> ---
> arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 3 ---
> 1 file changed, 3 deletions(-)
>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 4/9] riscv: dts: microchip: Group tuples in interrupt properties
2021-11-25 15:31 [PATCH 0/9] riscv: dts: Miscellaneous fixes Geert Uytterhoeven
` (2 preceding siblings ...)
2021-11-25 15:31 ` [PATCH 3/9] riscv: dts: microchip: mpfs: Drop empty chosen node Geert Uytterhoeven
@ 2021-11-25 15:31 ` Geert Uytterhoeven
2021-11-26 8:42 ` Conor.Dooley
2021-11-26 9:52 ` Krzysztof Kozlowski
2021-11-25 15:31 ` [PATCH 5/9] riscv: dts: microchip: mpfs: Fix PLIC node Geert Uytterhoeven
` (4 subsequent siblings)
8 siblings, 2 replies; 32+ messages in thread
From: Geert Uytterhoeven @ 2021-11-25 15:31 UTC (permalink / raw)
To: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Damien Le Moal, Lewis Hanly, Krzysztof Kozlowski, Conor Dooley
Cc: devicetree, linux-riscv, Geert Uytterhoeven
To improve human readability and enable automatic validation, the tuples
in the various properties containing interrupt specifiers should be
grouped.
Fix this by grouping the tuples of "interrupts" and
"interrupts-extended" properties using angle brackets.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
---
.../boot/dts/microchip/microchip-mpfs.dtsi | 31 ++++++++++---------
1 file changed, 16 insertions(+), 15 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index 794da883acb19256..d91226bfa586cda7 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -153,18 +153,18 @@ cache-controller@2010000 {
cache-size = <2097152>;
cache-unified;
interrupt-parent = <&plic>;
- interrupts = <1 2 3>;
+ interrupts = <1>, <2>, <3>;
reg = <0x0 0x2010000 0x0 0x1000>;
};
clint@2000000 {
compatible = "sifive,fu540-c000-clint", "sifive,clint0";
reg = <0x0 0x2000000 0x0 0xC000>;
- interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
- &cpu1_intc 3 &cpu1_intc 7
- &cpu2_intc 3 &cpu2_intc 7
- &cpu3_intc 3 &cpu3_intc 7
- &cpu4_intc 3 &cpu4_intc 7>;
+ interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
+ <&cpu1_intc 3>, <&cpu1_intc 7>,
+ <&cpu2_intc 3>, <&cpu2_intc 7>,
+ <&cpu3_intc 3>, <&cpu3_intc 7>,
+ <&cpu4_intc 3>, <&cpu4_intc 7>;
};
plic: interrupt-controller@c000000 {
@@ -173,18 +173,19 @@ plic: interrupt-controller@c000000 {
reg = <0x0 0xc000000 0x0 0x4000000>;
riscv,ndev = <186>;
interrupt-controller;
- interrupts-extended = <&cpu0_intc 11
- &cpu1_intc 11 &cpu1_intc 9
- &cpu2_intc 11 &cpu2_intc 9
- &cpu3_intc 11 &cpu3_intc 9
- &cpu4_intc 11 &cpu4_intc 9>;
+ interrupts-extended = <&cpu0_intc 11>,
+ <&cpu1_intc 11>, <&cpu1_intc 9>,
+ <&cpu2_intc 11>, <&cpu2_intc 9>,
+ <&cpu3_intc 11>, <&cpu3_intc 9>,
+ <&cpu4_intc 11>, <&cpu4_intc 9>;
};
dma@3000000 {
compatible = "sifive,fu540-c000-pdma";
reg = <0x0 0x3000000 0x0 0x8000>;
interrupt-parent = <&plic>;
- interrupts = <23 24 25 26 27 28 29 30>;
+ interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
+ <30>;
#dma-cells = <1>;
};
@@ -264,7 +265,7 @@ mmc: mmc@20008000 {
compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc";
reg = <0x0 0x20008000 0x0 0x1000>;
interrupt-parent = <&plic>;
- interrupts = <88 89>;
+ interrupts = <88>, <89>;
clocks = <&clkcfg 6>;
max-frequency = <200000000>;
status = "disabled";
@@ -274,7 +275,7 @@ emac0: ethernet@20110000 {
compatible = "cdns,macb";
reg = <0x0 0x20110000 0x0 0x2000>;
interrupt-parent = <&plic>;
- interrupts = <64 65 66 67>;
+ interrupts = <64>, <65>, <66>, <67>;
local-mac-address = [00 00 00 00 00 00];
clocks = <&clkcfg 4>, <&clkcfg 2>;
clock-names = "pclk", "hclk";
@@ -287,7 +288,7 @@ emac1: ethernet@20112000 {
compatible = "cdns,macb";
reg = <0x0 0x20112000 0x0 0x2000>;
interrupt-parent = <&plic>;
- interrupts = <70 71 72 73>;
+ interrupts = <70>, <71>, <72>, <73>;
local-mac-address = [00 00 00 00 00 00];
clocks = <&clkcfg 5>, <&clkcfg 2>;
status = "disabled";
--
2.25.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH 4/9] riscv: dts: microchip: Group tuples in interrupt properties
2021-11-25 15:31 ` [PATCH 4/9] riscv: dts: microchip: Group tuples in interrupt properties Geert Uytterhoeven
@ 2021-11-26 8:42 ` Conor.Dooley
2021-12-03 14:38 ` Geert Uytterhoeven
2021-11-26 9:52 ` Krzysztof Kozlowski
1 sibling, 1 reply; 32+ messages in thread
From: Conor.Dooley @ 2021-11-26 8:42 UTC (permalink / raw)
To: geert, robh+dt, paul.walmsley, palmer, aou, damien.lemoal,
Lewis.Hanly, krzysztof.kozlowski
Cc: devicetree, linux-riscv
On 25/11/2021 15:31, Geert Uytterhoeven wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> To improve human readability and enable automatic validation, the tuples
> in the various properties containing interrupt specifiers should be
> grouped.
>
> Fix this by grouping the tuples of "interrupts" and
> "interrupts-extended" properties using angle brackets.
Hi Geert,
I notice most of the icicle kit patches in this series were feedback
items from you on my series. I am assuming your intent is that I drop
those from my V2 (which should've been here by now but other things got
in the way) and base on this?
Thanks,
Conor.
>
> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
> ---
> .../boot/dts/microchip/microchip-mpfs.dtsi | 31 ++++++++++---------
> 1 file changed, 16 insertions(+), 15 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> index 794da883acb19256..d91226bfa586cda7 100644
> --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> @@ -153,18 +153,18 @@ cache-controller@2010000 {
> cache-size = <2097152>;
> cache-unified;
> interrupt-parent = <&plic>;
> - interrupts = <1 2 3>;
> + interrupts = <1>, <2>, <3>;
> reg = <0x0 0x2010000 0x0 0x1000>;
> };
>
> clint@2000000 {
> compatible = "sifive,fu540-c000-clint", "sifive,clint0";
> reg = <0x0 0x2000000 0x0 0xC000>;
> - interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
> - &cpu1_intc 3 &cpu1_intc 7
> - &cpu2_intc 3 &cpu2_intc 7
> - &cpu3_intc 3 &cpu3_intc 7
> - &cpu4_intc 3 &cpu4_intc 7>;
> + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
> + <&cpu1_intc 3>, <&cpu1_intc 7>,
> + <&cpu2_intc 3>, <&cpu2_intc 7>,
> + <&cpu3_intc 3>, <&cpu3_intc 7>,
> + <&cpu4_intc 3>, <&cpu4_intc 7>;
> };
>
> plic: interrupt-controller@c000000 {
> @@ -173,18 +173,19 @@ plic: interrupt-controller@c000000 {
> reg = <0x0 0xc000000 0x0 0x4000000>;
> riscv,ndev = <186>;
> interrupt-controller;
> - interrupts-extended = <&cpu0_intc 11
> - &cpu1_intc 11 &cpu1_intc 9
> - &cpu2_intc 11 &cpu2_intc 9
> - &cpu3_intc 11 &cpu3_intc 9
> - &cpu4_intc 11 &cpu4_intc 9>;
> + interrupts-extended = <&cpu0_intc 11>,
> + <&cpu1_intc 11>, <&cpu1_intc 9>,
> + <&cpu2_intc 11>, <&cpu2_intc 9>,
> + <&cpu3_intc 11>, <&cpu3_intc 9>,
> + <&cpu4_intc 11>, <&cpu4_intc 9>;
> };
>
> dma@3000000 {
> compatible = "sifive,fu540-c000-pdma";
> reg = <0x0 0x3000000 0x0 0x8000>;
> interrupt-parent = <&plic>;
> - interrupts = <23 24 25 26 27 28 29 30>;
> + interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
> + <30>;
> #dma-cells = <1>;
> };
>
> @@ -264,7 +265,7 @@ mmc: mmc@20008000 {
> compatible = "microchip,mpfs-sd4hc", "cdns,sd4hc";
> reg = <0x0 0x20008000 0x0 0x1000>;
> interrupt-parent = <&plic>;
> - interrupts = <88 89>;
> + interrupts = <88>, <89>;
> clocks = <&clkcfg 6>;
> max-frequency = <200000000>;
> status = "disabled";
> @@ -274,7 +275,7 @@ emac0: ethernet@20110000 {
> compatible = "cdns,macb";
> reg = <0x0 0x20110000 0x0 0x2000>;
> interrupt-parent = <&plic>;
> - interrupts = <64 65 66 67>;
> + interrupts = <64>, <65>, <66>, <67>;
> local-mac-address = [00 00 00 00 00 00];
> clocks = <&clkcfg 4>, <&clkcfg 2>;
> clock-names = "pclk", "hclk";
> @@ -287,7 +288,7 @@ emac1: ethernet@20112000 {
> compatible = "cdns,macb";
> reg = <0x0 0x20112000 0x0 0x2000>;
> interrupt-parent = <&plic>;
> - interrupts = <70 71 72 73>;
> + interrupts = <70>, <71>, <72>, <73>;
> local-mac-address = [00 00 00 00 00 00];
> clocks = <&clkcfg 5>, <&clkcfg 2>;
> status = "disabled";
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH 4/9] riscv: dts: microchip: Group tuples in interrupt properties
2021-11-26 8:42 ` Conor.Dooley
@ 2021-12-03 14:38 ` Geert Uytterhoeven
2021-12-03 15:17 ` Conor.Dooley
0 siblings, 1 reply; 32+ messages in thread
From: Geert Uytterhoeven @ 2021-12-03 14:38 UTC (permalink / raw)
To: Conor Dooley
Cc: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Damien Le Moal, Lewis Hanly, Krzysztof Kozlowski,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
linux-riscv
Hi Conor,
On Fri, Nov 26, 2021 at 9:42 AM <Conor.Dooley@microchip.com> wrote:
> On 25/11/2021 15:31, Geert Uytterhoeven wrote:
> > EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
> > To improve human readability and enable automatic validation, the tuples
> > in the various properties containing interrupt specifiers should be
> > grouped.
> >
> > Fix this by grouping the tuples of "interrupts" and
> > "interrupts-extended" properties using angle brackets.
> I notice most of the icicle kit patches in this series were feedback
> items from you on my series. I am assuming your intent is that I drop
Yeah, when I commented on your series, I already had made most of
these changes to my tree, but they were in an unfinished state.
> those from my V2 (which should've been here by now but other things got
> in the way) and base on this?
That may indeed be the easiest solution: fix existing issues first, then
enable more features.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH 4/9] riscv: dts: microchip: Group tuples in interrupt properties
2021-12-03 14:38 ` Geert Uytterhoeven
@ 2021-12-03 15:17 ` Conor.Dooley
0 siblings, 0 replies; 32+ messages in thread
From: Conor.Dooley @ 2021-12-03 15:17 UTC (permalink / raw)
To: geert
Cc: robh+dt, paul.walmsley, palmer, aou, damien.lemoal, Lewis.Hanly,
krzysztof.kozlowski, devicetree, linux-riscv
On 03/12/2021 14:38, Geert Uytterhoeven wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Hi Conor,
>
> On Fri, Nov 26, 2021 at 9:42 AM <Conor.Dooley@microchip.com> wrote:
>> On 25/11/2021 15:31, Geert Uytterhoeven wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>> To improve human readability and enable automatic validation, the tuples
>>> in the various properties containing interrupt specifiers should be
>>> grouped.
>>>
>>> Fix this by grouping the tuples of "interrupts" and
>>> "interrupts-extended" properties using angle brackets.
>
>> I notice most of the icicle kit patches in this series were feedback
>> items from you on my series. I am assuming your intent is that I drop
>
> Yeah, when I commented on your series, I already had made most of
> these changes to my tree, but they were in an unfinished state.
>
>> those from my V2 (which should've been here by now but other things got
>> in the way) and base on this?
>
> That may indeed be the easiest solution: fix existing issues first, then
> enable more features.
Aye, sounds good to me.
And since I did build/boot etc with this series:
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 4/9] riscv: dts: microchip: Group tuples in interrupt properties
2021-11-25 15:31 ` [PATCH 4/9] riscv: dts: microchip: Group tuples in interrupt properties Geert Uytterhoeven
2021-11-26 8:42 ` Conor.Dooley
@ 2021-11-26 9:52 ` Krzysztof Kozlowski
1 sibling, 0 replies; 32+ messages in thread
From: Krzysztof Kozlowski @ 2021-11-26 9:52 UTC (permalink / raw)
To: Geert Uytterhoeven, Rob Herring, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Damien Le Moal, Lewis Hanly, Conor Dooley
Cc: devicetree, linux-riscv
On 25/11/2021 16:31, Geert Uytterhoeven wrote:
> To improve human readability and enable automatic validation, the tuples
> in the various properties containing interrupt specifiers should be
> grouped.
>
> Fix this by grouping the tuples of "interrupts" and
> "interrupts-extended" properties using angle brackets.
>
> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
> ---
> .../boot/dts/microchip/microchip-mpfs.dtsi | 31 ++++++++++---------
> 1 file changed, 16 insertions(+), 15 deletions(-)
>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 5/9] riscv: dts: microchip: mpfs: Fix PLIC node
2021-11-25 15:31 [PATCH 0/9] riscv: dts: Miscellaneous fixes Geert Uytterhoeven
` (3 preceding siblings ...)
2021-11-25 15:31 ` [PATCH 4/9] riscv: dts: microchip: Group tuples in interrupt properties Geert Uytterhoeven
@ 2021-11-25 15:31 ` Geert Uytterhoeven
2021-11-26 9:49 ` Krzysztof Kozlowski
2021-11-26 11:49 ` Conor.Dooley
2021-11-25 15:31 ` [PATCH 6/9] riscv: dts: microchip: mpfs: Fix reference clock node Geert Uytterhoeven
` (3 subsequent siblings)
8 siblings, 2 replies; 32+ messages in thread
From: Geert Uytterhoeven @ 2021-11-25 15:31 UTC (permalink / raw)
To: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Damien Le Moal, Lewis Hanly, Krzysztof Kozlowski, Conor Dooley
Cc: devicetree, linux-riscv, Geert Uytterhoeven
Fix the device node for the Platform-Level Interrupt Controller (PLIC):
- Add missing "#address-cells" property,
- Sort properties according to DT bindings.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
---
arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index d91226bfa586cda7..c71d2d682fc0a0e7 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -168,16 +168,17 @@ clint@2000000 {
};
plic: interrupt-controller@c000000 {
- #interrupt-cells = <1>;
compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
reg = <0x0 0xc000000 0x0 0x4000000>;
- riscv,ndev = <186>;
+ #address-cells = <0>;
+ #interrupt-cells = <1>;
interrupt-controller;
interrupts-extended = <&cpu0_intc 11>,
<&cpu1_intc 11>, <&cpu1_intc 9>,
<&cpu2_intc 11>, <&cpu2_intc 9>,
<&cpu3_intc 11>, <&cpu3_intc 9>,
<&cpu4_intc 11>, <&cpu4_intc 9>;
+ riscv,ndev = <186>;
};
dma@3000000 {
--
2.25.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH 5/9] riscv: dts: microchip: mpfs: Fix PLIC node
2021-11-25 15:31 ` [PATCH 5/9] riscv: dts: microchip: mpfs: Fix PLIC node Geert Uytterhoeven
@ 2021-11-26 9:49 ` Krzysztof Kozlowski
2021-11-26 11:49 ` Conor.Dooley
1 sibling, 0 replies; 32+ messages in thread
From: Krzysztof Kozlowski @ 2021-11-26 9:49 UTC (permalink / raw)
To: Geert Uytterhoeven, Rob Herring, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Damien Le Moal, Lewis Hanly, Conor Dooley
Cc: devicetree, linux-riscv
On 25/11/2021 16:31, Geert Uytterhoeven wrote:
> Fix the device node for the Platform-Level Interrupt Controller (PLIC):
> - Add missing "#address-cells" property,
> - Sort properties according to DT bindings.
>
> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
> ---
> arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
And similar for fu540-c000.dtsi?
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 32+ messages in thread
* Re: [PATCH 5/9] riscv: dts: microchip: mpfs: Fix PLIC node
2021-11-25 15:31 ` [PATCH 5/9] riscv: dts: microchip: mpfs: Fix PLIC node Geert Uytterhoeven
2021-11-26 9:49 ` Krzysztof Kozlowski
@ 2021-11-26 11:49 ` Conor.Dooley
1 sibling, 0 replies; 32+ messages in thread
From: Conor.Dooley @ 2021-11-26 11:49 UTC (permalink / raw)
To: geert, robh+dt, paul.walmsley, palmer, aou, damien.lemoal,
Lewis.Hanly, krzysztof.kozlowski
Cc: devicetree, linux-riscv
On 25/11/2021 15:31, Geert Uytterhoeven wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> Fix the device node for the Platform-Level Interrupt Controller (PLIC):
> - Add missing "#address-cells" property,
> - Sort properties according to DT bindings.
>
> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
> ---
> arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>
> diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> index d91226bfa586cda7..c71d2d682fc0a0e7 100644
> --- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> +++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
> @@ -168,16 +168,17 @@ clint@2000000 {
> };
>
> plic: interrupt-controller@c000000 {
> - #interrupt-cells = <1>;
> compatible = "sifive,fu540-c000-plic", "sifive,plic-1.0.0";
> reg = <0x0 0xc000000 0x0 0x4000000>;
> - riscv,ndev = <186>;
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> interrupt-controller;
> interrupts-extended = <&cpu0_intc 11>,
> <&cpu1_intc 11>, <&cpu1_intc 9>,
> <&cpu2_intc 11>, <&cpu2_intc 9>,
> <&cpu3_intc 11>, <&cpu3_intc 9>,
> <&cpu4_intc 11>, <&cpu4_intc 9>;
> + riscv,ndev = <186>;
> };
>
> dma@3000000 {
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 6/9] riscv: dts: microchip: mpfs: Fix reference clock node
2021-11-25 15:31 [PATCH 0/9] riscv: dts: Miscellaneous fixes Geert Uytterhoeven
` (4 preceding siblings ...)
2021-11-25 15:31 ` [PATCH 5/9] riscv: dts: microchip: mpfs: Fix PLIC node Geert Uytterhoeven
@ 2021-11-25 15:31 ` Geert Uytterhoeven
2021-11-26 9:48 ` Krzysztof Kozlowski
2021-11-25 15:31 ` [PATCH 7/9] riscv: dts: sifive: Group tuples in register properties Geert Uytterhoeven
` (2 subsequent siblings)
8 siblings, 1 reply; 32+ messages in thread
From: Geert Uytterhoeven @ 2021-11-25 15:31 UTC (permalink / raw)
To: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Damien Le Moal, Lewis Hanly, Krzysztof Kozlowski, Conor Dooley
Cc: devicetree, linux-riscv, Geert Uytterhoeven
"make dtbs_check" reports:
arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dt.yaml: soc: refclk: {'compatible': ['fixed-clock'], '#clock-cells': [[0]], 'clock-frequency': [[600000000]], 'clock-output-names': ['msspllclk'], 'phandle': [[7]]} should not be valid under {'type': 'object'}
From schema: dtschema/schemas/simple-bus.yaml
Fix this by moving the node out of the "soc" subnode.
While at it, rename it to "msspllclk", and drop the now superfluous
"clock-output-names" property.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
---
arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 13 ++++++-------
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
index c71d2d682fc0a0e7..893864cf2447a9d4 100644
--- a/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
+++ b/arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi
@@ -139,6 +139,12 @@ cpu4_intc: interrupt-controller {
};
};
+ refclk: msspllclk {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <600000000>;
+ };
+
soc {
#address-cells = <2>;
#size-cells = <2>;
@@ -190,13 +196,6 @@ dma@3000000 {
#dma-cells = <1>;
};
- refclk: refclk {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- clock-frequency = <600000000>;
- clock-output-names = "msspllclk";
- };
-
clkcfg: clkcfg@20002000 {
compatible = "microchip,mpfs-clkcfg";
reg = <0x0 0x20002000 0x0 0x1000>;
--
2.25.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH 6/9] riscv: dts: microchip: mpfs: Fix reference clock node
2021-11-25 15:31 ` [PATCH 6/9] riscv: dts: microchip: mpfs: Fix reference clock node Geert Uytterhoeven
@ 2021-11-26 9:48 ` Krzysztof Kozlowski
2021-11-26 10:14 ` Conor.Dooley
0 siblings, 1 reply; 32+ messages in thread
From: Krzysztof Kozlowski @ 2021-11-26 9:48 UTC (permalink / raw)
To: Geert Uytterhoeven, Rob Herring, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Damien Le Moal, Lewis Hanly, Conor Dooley
Cc: devicetree, linux-riscv
On 25/11/2021 16:31, Geert Uytterhoeven wrote:
> "make dtbs_check" reports:
>
> arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dt.yaml: soc: refclk: {'compatible': ['fixed-clock'], '#clock-cells': [[0]], 'clock-frequency': [[600000000]], 'clock-output-names': ['msspllclk'], 'phandle': [[7]]} should not be valid under {'type': 'object'}
> From schema: dtschema/schemas/simple-bus.yaml
>
> Fix this by moving the node out of the "soc" subnode.
> While at it, rename it to "msspllclk", and drop the now superfluous
> "clock-output-names" property.
>
> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
> ---
> arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 13 ++++++-------
> 1 file changed, 6 insertions(+), 7 deletions(-)
>
It is also logical because refclk usually is not a property of the SoC.
It actually might be a property of board...
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH 6/9] riscv: dts: microchip: mpfs: Fix reference clock node
2021-11-26 9:48 ` Krzysztof Kozlowski
@ 2021-11-26 10:14 ` Conor.Dooley
2021-11-26 10:47 ` Conor.Dooley
2021-12-03 15:29 ` Conor.Dooley
0 siblings, 2 replies; 32+ messages in thread
From: Conor.Dooley @ 2021-11-26 10:14 UTC (permalink / raw)
To: krzysztof.kozlowski, geert, robh+dt, paul.walmsley, palmer, aou,
damien.lemoal, Lewis.Hanly
Cc: devicetree, linux-riscv
On 26/11/2021 09:48, Krzysztof Kozlowski wrote:
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> On 25/11/2021 16:31, Geert Uytterhoeven wrote:
>> "make dtbs_check" reports:
>>
>> arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dt.yaml: soc: refclk: {'compatible': ['fixed-clock'], '#clock-cells': [[0]], 'clock-frequency': [[600000000]], 'clock-output-names': ['msspllclk'], 'phandle': [[7]]} should not be valid under {'type': 'object'}
>> From schema: dtschema/schemas/simple-bus.yaml
>>
>> Fix this by moving the node out of the "soc" subnode.
>> While at it, rename it to "msspllclk", and drop the now superfluous
>> "clock-output-names" property.
>>
>> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
>> ---
>> arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 13 ++++++-------
>> 1 file changed, 6 insertions(+), 7 deletions(-)
>>
>
> It is also logical because refclk usually is not a property of the SoC.
> It actually might be a property of board...
This is one of the fun FPGAisms like the GPIO interrupt configuration.
This clock setting is determined by what design has been loaded onto the
FPGA - the msspll outputs are configurable, I could redo my FPGA design
and change this to 500 MHz etc. In turn the msspll clock is set by
another clock source that is actually on the board of either 100 or 125 MHz.
Since it's not set at bitstream programming time, I would agree that
that property should be moved to out of mpfs.dtsi.
>
>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
>
>
> Best regards,
> Krzysztof
>
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH 6/9] riscv: dts: microchip: mpfs: Fix reference clock node
2021-11-26 10:14 ` Conor.Dooley
@ 2021-11-26 10:47 ` Conor.Dooley
2021-12-03 15:29 ` Conor.Dooley
1 sibling, 0 replies; 32+ messages in thread
From: Conor.Dooley @ 2021-11-26 10:47 UTC (permalink / raw)
To: krzysztof.kozlowski, geert, robh+dt, paul.walmsley, palmer, aou,
damien.lemoal, Lewis.Hanly
Cc: devicetree, linux-riscv
On 26/11/2021 10:16, conor wrote:
> On 26/11/2021 09:48, Krzysztof Kozlowski wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know
>> the content is safe
>>
>> On 25/11/2021 16:31, Geert Uytterhoeven wrote:
>>> "make dtbs_check" reports:
>>>
>>> arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dt.yaml:
>>> soc: refclk: {'compatible': ['fixed-clock'], '#clock-cells': [[0]],
>>> 'clock-frequency': [[600000000]], 'clock-output-names':
>>> ['msspllclk'], 'phandle': [[7]]} should not be valid under {'type':
>>> 'object'}
>>> From schema: dtschema/schemas/simple-bus.yaml
>>>
>>> Fix this by moving the node out of the "soc" subnode.
>>> While at it, rename it to "msspllclk", and drop the now superfluous
>>> "clock-output-names" property.
>>>
>>> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
>>> ---
>>> arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 13 ++++++-------
>>> 1 file changed, 6 insertions(+), 7 deletions(-)
>>>
>>
>> It is also logical because refclk usually is not a property of the SoC.
>> It actually might be a property of board...
> This is one of the fun FPGAisms like the GPIO interrupt configuration.
> This clock setting is determined by what design has been loaded onto the
> FPGA - the msspll outputs are configurable, I could redo my FPGA design
> and change this to 500 MHz etc. In turn the msspll clock is set by
> another clock source that is actually on the board of either 100 or 125
> MHz.
>
> Since it's not set at bitstream programming time, I would agree that
> that property should be moved to out of mpfs.dtsi.
Since it's not set **UNTIL** bitstream programming time
>>
>>
>> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
>>
>>
>> Best regards,
>> Krzysztof
>>
>
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH 6/9] riscv: dts: microchip: mpfs: Fix reference clock node
2021-11-26 10:14 ` Conor.Dooley
2021-11-26 10:47 ` Conor.Dooley
@ 2021-12-03 15:29 ` Conor.Dooley
2021-12-03 15:42 ` Krzysztof Kozlowski
2021-12-03 15:49 ` Geert Uytterhoeven
1 sibling, 2 replies; 32+ messages in thread
From: Conor.Dooley @ 2021-12-03 15:29 UTC (permalink / raw)
To: krzysztof.kozlowski, geert
Cc: devicetree, palmer, linux-riscv, aou, paul.walmsley, robh+dt,
damien.lemoal, Lewis.Hanly
On 26/11/2021 10:16, conor wrote:
> On 26/11/2021 09:48, Krzysztof Kozlowski wrote:
>> EXTERNAL EMAIL: Do not click links or open attachments unless you know
>> the content is safe
>>
>> On 25/11/2021 16:31, Geert Uytterhoeven wrote:
>>> "make dtbs_check" reports:
>>>
>>> arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dt.yaml:
>>> soc: refclk: {'compatible': ['fixed-clock'], '#clock-cells': [[0]],
>>> 'clock-frequency': [[600000000]], 'clock-output-names':
>>> ['msspllclk'], 'phandle': [[7]]} should not be valid under {'type':
>>> 'object'}
>>> From schema: dtschema/schemas/simple-bus.yaml
>>>
>>> Fix this by moving the node out of the "soc" subnode.
>>> While at it, rename it to "msspllclk", and drop the now superfluous
>>> "clock-output-names" property.
>>>
>>> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
>>> ---
>>> arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 13 ++++++-------
>>> 1 file changed, 6 insertions(+), 7 deletions(-)
>>>
>>
>> It is also logical because refclk usually is not a property of the SoC.
>> It actually might be a property of board...
> This is one of the fun FPGAisms like the GPIO interrupt configuration.
> This clock setting is determined by what design has been loaded onto the
> FPGA - the msspll outputs are configurable, I could redo my FPGA design
> and change this to 500 MHz etc. In turn the msspll clock is set by
> another clock source that is actually on the board of either 100 or 125
> MHz.
>
> Since it's not set until bitstream programming time, I would agree that
> that property should be moved to out of mpfs.dtsi. (typo fixed)
Geert/Krzysztof,
Would the following make sense:
- Since the refclk hardware is a part of the chip, move the refclk out
of the soc node but leave it in mfps.dtsi
- The clk freq itself is set by the fpga bitstream, so move the
clock-frequency property to mpfs-icicle-kit.dts?
>>
>>
>> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
>>
>>
>> Best regards,
>> Krzysztof
>>
>
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH 6/9] riscv: dts: microchip: mpfs: Fix reference clock node
2021-12-03 15:29 ` Conor.Dooley
@ 2021-12-03 15:42 ` Krzysztof Kozlowski
2021-12-03 15:49 ` Geert Uytterhoeven
1 sibling, 0 replies; 32+ messages in thread
From: Krzysztof Kozlowski @ 2021-12-03 15:42 UTC (permalink / raw)
To: Conor.Dooley, geert
Cc: devicetree, palmer, linux-riscv, aou, paul.walmsley, robh+dt,
damien.lemoal, Lewis.Hanly
On 03/12/2021 16:29, Conor.Dooley@microchip.com wrote:
> On 26/11/2021 10:16, conor wrote:
>> On 26/11/2021 09:48, Krzysztof Kozlowski wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know
>>> the content is safe
>>>
>>> On 25/11/2021 16:31, Geert Uytterhoeven wrote:
>>>> "make dtbs_check" reports:
>>>>
>>>> arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dt.yaml:
>>>> soc: refclk: {'compatible': ['fixed-clock'], '#clock-cells': [[0]],
>>>> 'clock-frequency': [[600000000]], 'clock-output-names':
>>>> ['msspllclk'], 'phandle': [[7]]} should not be valid under {'type':
>>>> 'object'}
>>>> From schema: dtschema/schemas/simple-bus.yaml
>>>>
>>>> Fix this by moving the node out of the "soc" subnode.
>>>> While at it, rename it to "msspllclk", and drop the now superfluous
>>>> "clock-output-names" property.
>>>>
>>>> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
>>>> ---
>>>> arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 13 ++++++-------
>>>> 1 file changed, 6 insertions(+), 7 deletions(-)
>>>>
>>>
>>> It is also logical because refclk usually is not a property of the SoC.
>>> It actually might be a property of board...
>> This is one of the fun FPGAisms like the GPIO interrupt configuration.
>> This clock setting is determined by what design has been loaded onto the
>> FPGA - the msspll outputs are configurable, I could redo my FPGA design
>> and change this to 500 MHz etc. In turn the msspll clock is set by
>> another clock source that is actually on the board of either 100 or 125
>> MHz.
>>
>> Since it's not set until bitstream programming time, I would agree that
>> that property should be moved to out of mpfs.dtsi. (typo fixed)
> Geert/Krzysztof,
> Would the following make sense:
> - Since the refclk hardware is a part of the chip, move the refclk out
> of the soc node but leave it in mfps.dtsi
> - The clk freq itself is set by the fpga bitstream, so move the
> clock-frequency property to mpfs-icicle-kit.dts?
Yes, makes sense to me.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 32+ messages in thread* Re: [PATCH 6/9] riscv: dts: microchip: mpfs: Fix reference clock node
2021-12-03 15:29 ` Conor.Dooley
2021-12-03 15:42 ` Krzysztof Kozlowski
@ 2021-12-03 15:49 ` Geert Uytterhoeven
1 sibling, 0 replies; 32+ messages in thread
From: Geert Uytterhoeven @ 2021-12-03 15:49 UTC (permalink / raw)
To: Conor Dooley
Cc: Krzysztof Kozlowski,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Palmer Dabbelt, linux-riscv, Albert Ou, Paul Walmsley,
Rob Herring, Damien Le Moal, Lewis Hanly
Hi Conor,
On Fri, Dec 3, 2021 at 4:30 PM <Conor.Dooley@microchip.com> wrote:
> On 26/11/2021 10:16, conor wrote:
> > On 26/11/2021 09:48, Krzysztof Kozlowski wrote:
> >> EXTERNAL EMAIL: Do not click links or open attachments unless you know
> >> the content is safe
> >> On 25/11/2021 16:31, Geert Uytterhoeven wrote:
> >>> "make dtbs_check" reports:
> >>>
> >>> arch/riscv/boot/dts/microchip/microchip-mpfs-icicle-kit.dt.yaml:
> >>> soc: refclk: {'compatible': ['fixed-clock'], '#clock-cells': [[0]],
> >>> 'clock-frequency': [[600000000]], 'clock-output-names':
> >>> ['msspllclk'], 'phandle': [[7]]} should not be valid under {'type':
> >>> 'object'}
> >>> From schema: dtschema/schemas/simple-bus.yaml
> >>>
> >>> Fix this by moving the node out of the "soc" subnode.
> >>> While at it, rename it to "msspllclk", and drop the now superfluous
> >>> "clock-output-names" property.
> >>>
> >>> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
> >>> ---
> >>> arch/riscv/boot/dts/microchip/microchip-mpfs.dtsi | 13 ++++++-------
> >>> 1 file changed, 6 insertions(+), 7 deletions(-)
> >>>
> >>
> >> It is also logical because refclk usually is not a property of the SoC.
> >> It actually might be a property of board...
> > This is one of the fun FPGAisms like the GPIO interrupt configuration.
> > This clock setting is determined by what design has been loaded onto the
> > FPGA - the msspll outputs are configurable, I could redo my FPGA design
> > and change this to 500 MHz etc. In turn the msspll clock is set by
> > another clock source that is actually on the board of either 100 or 125
> > MHz.
> >
> > Since it's not set until bitstream programming time, I would agree that
> > that property should be moved to out of mpfs.dtsi. (typo fixed)
>
> Geert/Krzysztof,
> Would the following make sense:
> - Since the refclk hardware is a part of the chip, move the refclk out
> of the soc node but leave it in mfps.dtsi
> - The clk freq itself is set by the fpga bitstream, so move the
> clock-frequency property to mpfs-icicle-kit.dts?
That was exactly what I had in mind when I read your previous email.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 7/9] riscv: dts: sifive: Group tuples in register properties
2021-11-25 15:31 [PATCH 0/9] riscv: dts: Miscellaneous fixes Geert Uytterhoeven
` (5 preceding siblings ...)
2021-11-25 15:31 ` [PATCH 6/9] riscv: dts: microchip: mpfs: Fix reference clock node Geert Uytterhoeven
@ 2021-11-25 15:31 ` Geert Uytterhoeven
2021-11-26 9:46 ` Krzysztof Kozlowski
2021-11-25 15:31 ` [PATCH 8/9] riscv: dts: sifive: Group tuples in interrupt properties Geert Uytterhoeven
2021-11-25 15:31 ` [PATCH 9/9] riscv: dts: sifive: fu540-c000: Drop bogus soc node compatible values Geert Uytterhoeven
8 siblings, 1 reply; 32+ messages in thread
From: Geert Uytterhoeven @ 2021-11-25 15:31 UTC (permalink / raw)
To: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Damien Le Moal, Lewis Hanly, Krzysztof Kozlowski, Conor Dooley
Cc: devicetree, linux-riscv, Geert Uytterhoeven
To improve human readability and enable automatic validation, the tuples
in "reg" properties containing register blocks should be grouped using
angle brackets.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
---
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
index 0655b5c4201d9f71..35d75a8aa8cc9031 100644
--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
@@ -195,8 +195,8 @@ i2c0: i2c@10030000 {
};
qspi0: spi@10040000 {
compatible = "sifive,fu540-c000-spi", "sifive,spi0";
- reg = <0x0 0x10040000 0x0 0x1000
- 0x0 0x20000000 0x0 0x10000000>;
+ reg = <0x0 0x10040000 0x0 0x1000>,
+ <0x0 0x20000000 0x0 0x10000000>;
interrupt-parent = <&plic0>;
interrupts = <51>;
clocks = <&prci PRCI_CLK_TLCLK>;
@@ -206,8 +206,8 @@ qspi0: spi@10040000 {
};
qspi1: spi@10041000 {
compatible = "sifive,fu540-c000-spi", "sifive,spi0";
- reg = <0x0 0x10041000 0x0 0x1000
- 0x0 0x30000000 0x0 0x10000000>;
+ reg = <0x0 0x10041000 0x0 0x1000>,
+ <0x0 0x30000000 0x0 0x10000000>;
interrupt-parent = <&plic0>;
interrupts = <52>;
clocks = <&prci PRCI_CLK_TLCLK>;
@@ -229,8 +229,8 @@ eth0: ethernet@10090000 {
compatible = "sifive,fu540-c000-gem";
interrupt-parent = <&plic0>;
interrupts = <53>;
- reg = <0x0 0x10090000 0x0 0x2000
- 0x0 0x100a0000 0x0 0x1000>;
+ reg = <0x0 0x10090000 0x0 0x2000>,
+ <0x0 0x100a0000 0x0 0x1000>;
local-mac-address = [00 00 00 00 00 00];
clock-names = "pclk", "hclk";
clocks = <&prci PRCI_CLK_GEMGXLPLL>,
--
2.25.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH 7/9] riscv: dts: sifive: Group tuples in register properties
2021-11-25 15:31 ` [PATCH 7/9] riscv: dts: sifive: Group tuples in register properties Geert Uytterhoeven
@ 2021-11-26 9:46 ` Krzysztof Kozlowski
0 siblings, 0 replies; 32+ messages in thread
From: Krzysztof Kozlowski @ 2021-11-26 9:46 UTC (permalink / raw)
To: Geert Uytterhoeven, Rob Herring, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Damien Le Moal, Lewis Hanly, Conor Dooley
Cc: devicetree, linux-riscv
On 25/11/2021 16:31, Geert Uytterhoeven wrote:
> To improve human readability and enable automatic validation, the tuples
> in "reg" properties containing register blocks should be grouped using
> angle brackets.
>
> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
> ---
> arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 12 ++++++------
> 1 file changed, 6 insertions(+), 6 deletions(-)
>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 8/9] riscv: dts: sifive: Group tuples in interrupt properties
2021-11-25 15:31 [PATCH 0/9] riscv: dts: Miscellaneous fixes Geert Uytterhoeven
` (6 preceding siblings ...)
2021-11-25 15:31 ` [PATCH 7/9] riscv: dts: sifive: Group tuples in register properties Geert Uytterhoeven
@ 2021-11-25 15:31 ` Geert Uytterhoeven
2021-11-26 9:46 ` Krzysztof Kozlowski
2021-11-25 15:31 ` [PATCH 9/9] riscv: dts: sifive: fu540-c000: Drop bogus soc node compatible values Geert Uytterhoeven
8 siblings, 1 reply; 32+ messages in thread
From: Geert Uytterhoeven @ 2021-11-25 15:31 UTC (permalink / raw)
To: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Damien Le Moal, Lewis Hanly, Krzysztof Kozlowski, Conor Dooley
Cc: devicetree, linux-riscv, Geert Uytterhoeven
To improve human readability and enable automatic validation, the tuples
in the various properties containing interrupt specifiers should be
grouped.
Fix this by grouping the tuples of "interrupts" and
"interrupts-extended" properties using angle brackets.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
---
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 21 +++++++++++----------
arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 14 +++++++-------
2 files changed, 18 insertions(+), 17 deletions(-)
diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
index 35d75a8aa8cc9031..e2efcf08210926f8 100644
--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
@@ -145,12 +145,12 @@ plic0: interrupt-controller@c000000 {
reg = <0x0 0xc000000 0x0 0x4000000>;
riscv,ndev = <53>;
interrupt-controller;
- interrupts-extended = <
- &cpu0_intc 0xffffffff
- &cpu1_intc 0xffffffff &cpu1_intc 9
- &cpu2_intc 0xffffffff &cpu2_intc 9
- &cpu3_intc 0xffffffff &cpu3_intc 9
- &cpu4_intc 0xffffffff &cpu4_intc 9>;
+ interrupts-extended =
+ <&cpu0_intc 0xffffffff>,
+ <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>,
+ <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>,
+ <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>,
+ <&cpu4_intc 0xffffffff>, <&cpu4_intc 9>;
};
prci: clock-controller@10000000 {
compatible = "sifive,fu540-c000-prci";
@@ -170,7 +170,8 @@ dma: dma@3000000 {
compatible = "sifive,fu540-c000-pdma";
reg = <0x0 0x3000000 0x0 0x8000>;
interrupt-parent = <&plic0>;
- interrupts = <23 24 25 26 27 28 29 30>;
+ interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
+ <30>;
#dma-cells = <1>;
};
uart1: serial@10011000 {
@@ -243,7 +244,7 @@ pwm0: pwm@10020000 {
compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
reg = <0x0 0x10020000 0x0 0x1000>;
interrupt-parent = <&plic0>;
- interrupts = <42 43 44 45>;
+ interrupts = <42>, <43>, <44>, <45>;
clocks = <&prci PRCI_CLK_TLCLK>;
#pwm-cells = <3>;
status = "disabled";
@@ -252,7 +253,7 @@ pwm1: pwm@10021000 {
compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
reg = <0x0 0x10021000 0x0 0x1000>;
interrupt-parent = <&plic0>;
- interrupts = <46 47 48 49>;
+ interrupts = <46>, <47>, <48>, <49>;
clocks = <&prci PRCI_CLK_TLCLK>;
#pwm-cells = <3>;
status = "disabled";
@@ -265,7 +266,7 @@ l2cache: cache-controller@2010000 {
cache-size = <2097152>;
cache-unified;
interrupt-parent = <&plic0>;
- interrupts = <1 2 3>;
+ interrupts = <1>, <2>, <3>;
reg = <0x0 0x2010000 0x0 0x1000>;
};
gpio: gpio@10060000 {
diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
index abbb960f90a00ac2..8464b0e3c88791e1 100644
--- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
@@ -147,12 +147,12 @@ plic0: interrupt-controller@c000000 {
reg = <0x0 0xc000000 0x0 0x4000000>;
riscv,ndev = <69>;
interrupt-controller;
- interrupts-extended = <
- &cpu0_intc 0xffffffff
- &cpu1_intc 0xffffffff &cpu1_intc 9
- &cpu2_intc 0xffffffff &cpu2_intc 9
- &cpu3_intc 0xffffffff &cpu3_intc 9
- &cpu4_intc 0xffffffff &cpu4_intc 9>;
+ interrupts-extended =
+ <&cpu0_intc 0xffffffff>,
+ <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>,
+ <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>,
+ <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>,
+ <&cpu4_intc 0xffffffff>, <&cpu4_intc 9>;
};
prci: clock-controller@10000000 {
compatible = "sifive,fu740-c000-prci";
@@ -273,7 +273,7 @@ ccache: cache-controller@2010000 {
cache-size = <2097152>;
cache-unified;
interrupt-parent = <&plic0>;
- interrupts = <19 21 22 20>;
+ interrupts = <19>, <21>, <22>, <20>;
reg = <0x0 0x2010000 0x0 0x1000>;
};
gpio: gpio@10060000 {
--
2.25.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH 8/9] riscv: dts: sifive: Group tuples in interrupt properties
2021-11-25 15:31 ` [PATCH 8/9] riscv: dts: sifive: Group tuples in interrupt properties Geert Uytterhoeven
@ 2021-11-26 9:46 ` Krzysztof Kozlowski
0 siblings, 0 replies; 32+ messages in thread
From: Krzysztof Kozlowski @ 2021-11-26 9:46 UTC (permalink / raw)
To: Geert Uytterhoeven, Rob Herring, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Damien Le Moal, Lewis Hanly, Conor Dooley
Cc: devicetree, linux-riscv
On 25/11/2021 16:31, Geert Uytterhoeven wrote:
> To improve human readability and enable automatic validation, the tuples
> in the various properties containing interrupt specifiers should be
> grouped.
>
> Fix this by grouping the tuples of "interrupts" and
> "interrupts-extended" properties using angle brackets.
>
> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
> ---
> arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 21 +++++++++++----------
> arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 14 +++++++-------
> 2 files changed, 18 insertions(+), 17 deletions(-)
>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 32+ messages in thread
* [PATCH 9/9] riscv: dts: sifive: fu540-c000: Drop bogus soc node compatible values
2021-11-25 15:31 [PATCH 0/9] riscv: dts: Miscellaneous fixes Geert Uytterhoeven
` (7 preceding siblings ...)
2021-11-25 15:31 ` [PATCH 8/9] riscv: dts: sifive: Group tuples in interrupt properties Geert Uytterhoeven
@ 2021-11-25 15:31 ` Geert Uytterhoeven
2021-11-26 9:46 ` Krzysztof Kozlowski
8 siblings, 1 reply; 32+ messages in thread
From: Geert Uytterhoeven @ 2021-11-25 15:31 UTC (permalink / raw)
To: Rob Herring, Paul Walmsley, Palmer Dabbelt, Albert Ou,
Damien Le Moal, Lewis Hanly, Krzysztof Kozlowski, Conor Dooley
Cc: devicetree, linux-riscv, Geert Uytterhoeven
"make dtbs_check":
arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml: soc: $nodename:0: '/' was expected
From schema: Documentation/devicetree/bindings/riscv/sifive.yaml
arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml: soc: compatible: 'oneOf' conditional failed, one must be fixed:
'sifive,fu540-c000' is not one of ['sifive,hifive-unleashed-a00']
'sifive,fu540-c000' is not one of ['sifive,hifive-unmatched-a00']
'sifive,fu540-c000' was expected
'sifive,fu740-c000' was expected
'sifive,fu540' was expected
'sifive,fu740' was expected
From schema: Documentation/devicetree/bindings/riscv/sifive.yaml
This happens because the "soc" subnode declares compatibility with
"sifive,fu540-c000" and "sifive,fu540", while these are only intended
for the root node.
Fix this by removing the bogus compatible values from the "soc" node.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
---
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
index e2efcf08210926f8..b1250c16816f5c9d 100644
--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
@@ -137,7 +137,7 @@ cpu4_intc: interrupt-controller {
soc {
#address-cells = <2>;
#size-cells = <2>;
- compatible = "sifive,fu540-c000", "sifive,fu540", "simple-bus";
+ compatible = "simple-bus";
ranges;
plic0: interrupt-controller@c000000 {
#interrupt-cells = <1>;
--
2.25.1
^ permalink raw reply related [flat|nested] 32+ messages in thread* Re: [PATCH 9/9] riscv: dts: sifive: fu540-c000: Drop bogus soc node compatible values
2021-11-25 15:31 ` [PATCH 9/9] riscv: dts: sifive: fu540-c000: Drop bogus soc node compatible values Geert Uytterhoeven
@ 2021-11-26 9:46 ` Krzysztof Kozlowski
0 siblings, 0 replies; 32+ messages in thread
From: Krzysztof Kozlowski @ 2021-11-26 9:46 UTC (permalink / raw)
To: Geert Uytterhoeven, Rob Herring, Paul Walmsley, Palmer Dabbelt,
Albert Ou, Damien Le Moal, Lewis Hanly, Conor Dooley
Cc: devicetree, linux-riscv
On 25/11/2021 16:31, Geert Uytterhoeven wrote:
> "make dtbs_check":
>
> arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml: soc: $nodename:0: '/' was expected
> From schema: Documentation/devicetree/bindings/riscv/sifive.yaml
> arch/riscv/boot/dts/sifive/hifive-unleashed-a00.dt.yaml: soc: compatible: 'oneOf' conditional failed, one must be fixed:
> 'sifive,fu540-c000' is not one of ['sifive,hifive-unleashed-a00']
> 'sifive,fu540-c000' is not one of ['sifive,hifive-unmatched-a00']
> 'sifive,fu540-c000' was expected
> 'sifive,fu740-c000' was expected
> 'sifive,fu540' was expected
> 'sifive,fu740' was expected
> From schema: Documentation/devicetree/bindings/riscv/sifive.yaml
>
> This happens because the "soc" subnode declares compatibility with
> "sifive,fu540-c000" and "sifive,fu540", while these are only intended
> for the root node.
>
> Fix this by removing the bogus compatible values from the "soc" node.
>
> Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
> ---
> arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 32+ messages in thread