From: Geert Uytterhoeven <geert@linux-m68k.org>
To: Rob Herring <robh+dt@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Damien Le Moal <damien.lemoal@wdc.com>,
Lewis Hanly <lewis.hanly@microchip.com>,
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
Conor Dooley <conor.dooley@microchip.com>
Cc: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
Geert Uytterhoeven <geert@linux-m68k.org>
Subject: [PATCH 8/9] riscv: dts: sifive: Group tuples in interrupt properties
Date: Thu, 25 Nov 2021 16:31:30 +0100 [thread overview]
Message-ID: <20211125153131.163533-9-geert@linux-m68k.org> (raw)
In-Reply-To: <20211125153131.163533-1-geert@linux-m68k.org>
To improve human readability and enable automatic validation, the tuples
in the various properties containing interrupt specifiers should be
grouped.
Fix this by grouping the tuples of "interrupts" and
"interrupts-extended" properties using angle brackets.
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
---
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 21 +++++++++++----------
arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 14 +++++++-------
2 files changed, 18 insertions(+), 17 deletions(-)
diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
index 35d75a8aa8cc9031..e2efcf08210926f8 100644
--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
@@ -145,12 +145,12 @@ plic0: interrupt-controller@c000000 {
reg = <0x0 0xc000000 0x0 0x4000000>;
riscv,ndev = <53>;
interrupt-controller;
- interrupts-extended = <
- &cpu0_intc 0xffffffff
- &cpu1_intc 0xffffffff &cpu1_intc 9
- &cpu2_intc 0xffffffff &cpu2_intc 9
- &cpu3_intc 0xffffffff &cpu3_intc 9
- &cpu4_intc 0xffffffff &cpu4_intc 9>;
+ interrupts-extended =
+ <&cpu0_intc 0xffffffff>,
+ <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>,
+ <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>,
+ <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>,
+ <&cpu4_intc 0xffffffff>, <&cpu4_intc 9>;
};
prci: clock-controller@10000000 {
compatible = "sifive,fu540-c000-prci";
@@ -170,7 +170,8 @@ dma: dma@3000000 {
compatible = "sifive,fu540-c000-pdma";
reg = <0x0 0x3000000 0x0 0x8000>;
interrupt-parent = <&plic0>;
- interrupts = <23 24 25 26 27 28 29 30>;
+ interrupts = <23>, <24>, <25>, <26>, <27>, <28>, <29>,
+ <30>;
#dma-cells = <1>;
};
uart1: serial@10011000 {
@@ -243,7 +244,7 @@ pwm0: pwm@10020000 {
compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
reg = <0x0 0x10020000 0x0 0x1000>;
interrupt-parent = <&plic0>;
- interrupts = <42 43 44 45>;
+ interrupts = <42>, <43>, <44>, <45>;
clocks = <&prci PRCI_CLK_TLCLK>;
#pwm-cells = <3>;
status = "disabled";
@@ -252,7 +253,7 @@ pwm1: pwm@10021000 {
compatible = "sifive,fu540-c000-pwm", "sifive,pwm0";
reg = <0x0 0x10021000 0x0 0x1000>;
interrupt-parent = <&plic0>;
- interrupts = <46 47 48 49>;
+ interrupts = <46>, <47>, <48>, <49>;
clocks = <&prci PRCI_CLK_TLCLK>;
#pwm-cells = <3>;
status = "disabled";
@@ -265,7 +266,7 @@ l2cache: cache-controller@2010000 {
cache-size = <2097152>;
cache-unified;
interrupt-parent = <&plic0>;
- interrupts = <1 2 3>;
+ interrupts = <1>, <2>, <3>;
reg = <0x0 0x2010000 0x0 0x1000>;
};
gpio: gpio@10060000 {
diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
index abbb960f90a00ac2..8464b0e3c88791e1 100644
--- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
@@ -147,12 +147,12 @@ plic0: interrupt-controller@c000000 {
reg = <0x0 0xc000000 0x0 0x4000000>;
riscv,ndev = <69>;
interrupt-controller;
- interrupts-extended = <
- &cpu0_intc 0xffffffff
- &cpu1_intc 0xffffffff &cpu1_intc 9
- &cpu2_intc 0xffffffff &cpu2_intc 9
- &cpu3_intc 0xffffffff &cpu3_intc 9
- &cpu4_intc 0xffffffff &cpu4_intc 9>;
+ interrupts-extended =
+ <&cpu0_intc 0xffffffff>,
+ <&cpu1_intc 0xffffffff>, <&cpu1_intc 9>,
+ <&cpu2_intc 0xffffffff>, <&cpu2_intc 9>,
+ <&cpu3_intc 0xffffffff>, <&cpu3_intc 9>,
+ <&cpu4_intc 0xffffffff>, <&cpu4_intc 9>;
};
prci: clock-controller@10000000 {
compatible = "sifive,fu740-c000-prci";
@@ -273,7 +273,7 @@ ccache: cache-controller@2010000 {
cache-size = <2097152>;
cache-unified;
interrupt-parent = <&plic0>;
- interrupts = <19 21 22 20>;
+ interrupts = <19>, <21>, <22>, <20>;
reg = <0x0 0x2010000 0x0 0x1000>;
};
gpio: gpio@10060000 {
--
2.25.1
next prev parent reply other threads:[~2021-11-25 15:41 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-11-25 15:31 [PATCH 0/9] riscv: dts: Miscellaneous fixes Geert Uytterhoeven
2021-11-25 15:31 ` [PATCH 1/9] riscv: dts: canaan: Fix SPI FLASH node names Geert Uytterhoeven
2021-11-26 4:41 ` Damien Le Moal
2021-11-26 9:54 ` Krzysztof Kozlowski
2021-11-25 15:31 ` [PATCH 2/9] riscv: dts: canaan: Group tuples in interrupt properties Geert Uytterhoeven
2021-11-26 4:42 ` Damien Le Moal
2021-11-26 9:53 ` Krzysztof Kozlowski
2021-11-25 15:31 ` [PATCH 3/9] riscv: dts: microchip: mpfs: Drop empty chosen node Geert Uytterhoeven
2021-11-26 9:53 ` Krzysztof Kozlowski
2021-11-26 9:57 ` Geert Uytterhoeven
2021-11-26 11:45 ` Conor.Dooley
2021-11-25 15:31 ` [PATCH 4/9] riscv: dts: microchip: Group tuples in interrupt properties Geert Uytterhoeven
2021-11-26 8:42 ` Conor.Dooley
2021-12-03 14:38 ` Geert Uytterhoeven
2021-12-03 15:17 ` Conor.Dooley
2021-11-26 9:52 ` Krzysztof Kozlowski
2021-11-25 15:31 ` [PATCH 5/9] riscv: dts: microchip: mpfs: Fix PLIC node Geert Uytterhoeven
2021-11-26 9:49 ` Krzysztof Kozlowski
2021-11-26 11:49 ` Conor.Dooley
2021-11-25 15:31 ` [PATCH 6/9] riscv: dts: microchip: mpfs: Fix reference clock node Geert Uytterhoeven
2021-11-26 9:48 ` Krzysztof Kozlowski
2021-11-26 10:14 ` Conor.Dooley
2021-11-26 10:47 ` Conor.Dooley
2021-12-03 15:29 ` Conor.Dooley
2021-12-03 15:42 ` Krzysztof Kozlowski
2021-12-03 15:49 ` Geert Uytterhoeven
2021-11-25 15:31 ` [PATCH 7/9] riscv: dts: sifive: Group tuples in register properties Geert Uytterhoeven
2021-11-26 9:46 ` Krzysztof Kozlowski
2021-11-25 15:31 ` Geert Uytterhoeven [this message]
2021-11-26 9:46 ` [PATCH 8/9] riscv: dts: sifive: Group tuples in interrupt properties Krzysztof Kozlowski
2021-11-25 15:31 ` [PATCH 9/9] riscv: dts: sifive: fu540-c000: Drop bogus soc node compatible values Geert Uytterhoeven
2021-11-26 9:46 ` Krzysztof Kozlowski
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