From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5AA07C433FE for ; Tue, 30 Nov 2021 14:06:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S241998AbhK3OJ6 (ORCPT ); Tue, 30 Nov 2021 09:09:58 -0500 Received: from esa.microchip.iphmx.com ([68.232.153.233]:3996 "EHLO esa.microchip.iphmx.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242008AbhK3OJq (ORCPT ); Tue, 30 Nov 2021 09:09:46 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1638281188; x=1669817188; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ISPiehvX29ycYUVk9nTnr4Tmhs1DnEQEzRlqhtiaKls=; b=ihcgA6LJ6lXQsXtuoQf1iUkgTiX8XF37fNyVwm8FHs3hsGfgOnvAIApG fMPUHn/cEnd/a7EPoRTQUm96m59TB7g5ELj88q8W073gHCnB3AEiNtaXS IoUnE8o4z3maIfgC1KphDOEJ7nHc3/YSV0r8HRaAWZDiqfRD6m2W5pOqQ Tn9VdjorOTFZuvwJvlp2jWRJpE6eoL3R0MgSzdtuvlTktnZDaKle1xLHg DA+cNNNjY2U0zqXjUMPek5LThTgau6VnX7bxW/YU3mmETcBvLrD2Saaaq gAb/GOEbcHpZqbocH5zNsxIixMZPqaIgMj0BhI19rqQ+QkjWmpUSxnTHq Q==; IronPort-SDR: lmIWF6ZcbfvSfgjuRTLOqSpPYOlIr5lwb/e/TXds4JgrBPBpTOyLvyFTXJAmjfyrGf/jCjEMC0 ZZ7qQ0+muGrMCzlCJE/yMtvAVcRyv1YTh7755ektOswlGr24rIHslLFayX9LLW1lEPtOGCsnV+ JTVU3HIiTizJraz1MV7pugGl+W3FtJ8od/82rwgFI6uDq6+5l/BcWBAFXwEOKOrFMnj+LF/8qF r9zlK3aqWWarEUVPxPMMnVtorADWNSQ51eHRJELrhNpzNbrqiJmOM6UYEk6zegOTa+NzEcbKoK 9q+bVr08WWd7Vm4c3QW6LdPs X-IronPort-AV: E=Sophos;i="5.87,276,1631602800"; d="scan'208";a="144989062" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa5.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 30 Nov 2021 07:06:22 -0700 Received: from chn-vm-ex03.mchp-main.com (10.10.85.151) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2176.14; Tue, 30 Nov 2021 07:06:21 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server id 15.1.2176.14 via Frontend Transport; Tue, 30 Nov 2021 07:06:19 -0700 From: To: , , , , CC: , , , , , , , Rob Herring Subject: [PATCH v6 1/2] dt-bindings: clk: microchip: Add Microchip PolarFire host binding Date: Tue, 30 Nov 2021 14:07:23 +0000 Message-ID: <20211130140724.10750-2-conor.dooley@microchip.com> X-Mailer: git-send-email 2.33.1 In-Reply-To: <20211130140724.10750-1-conor.dooley@microchip.com> References: <20211130140724.10750-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Daire McNamara Add device tree bindings for the Microchip PolarFire system clock controller Signed-off-by: Daire McNamara Signed-off-by: Conor Dooley Reviewed-by: Rob Herring --- .../bindings/clock/microchip,mpfs.yaml | 58 +++++++++++++++++++ .../dt-bindings/clock/microchip,mpfs-clock.h | 45 ++++++++++++++ 2 files changed, 103 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/microchip,mpfs.yaml create mode 100644 include/dt-bindings/clock/microchip,mpfs-clock.h diff --git a/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml b/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml new file mode 100644 index 000000000000..0c15afa2214c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/microchip,mpfs.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/microchip,mpfs.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PolarFire Clock Control Module Binding + +maintainers: + - Daire McNamara + +description: | + Microchip PolarFire clock control (CLKCFG) is an integrated clock controller, + which gates and enables all peripheral clocks. + + This device tree binding describes 33 gate clocks. Clocks are referenced by + user nodes by the CLKCFG node phandle and the clock index in the group, from + 0 to 32. + +properties: + compatible: + const: microchip,mpfs-clkcfg + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + '#clock-cells': + const: 1 + description: | + The clock consumer should specify the desired clock by having the clock + ID in its "clocks" phandle cell. See include/dt-bindings/clock/microchip,mpfs-clock.h + for the full list of PolarFire clock IDs. + +required: + - compatible + - reg + - clocks + - '#clock-cells' + +additionalProperties: false + +examples: + # Clock Config node: + - | + #include + soc { + #address-cells = <2>; + #size-cells = <2>; + clkcfg: clock-controller@20002000 { + compatible = "microchip,mpfs-clkcfg"; + reg = <0x0 0x20002000 0x0 0x1000>; + clocks = <&ref>; + #clock-cells = <1>; + }; + }; diff --git a/include/dt-bindings/clock/microchip,mpfs-clock.h b/include/dt-bindings/clock/microchip,mpfs-clock.h new file mode 100644 index 000000000000..73f2a9324857 --- /dev/null +++ b/include/dt-bindings/clock/microchip,mpfs-clock.h @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Daire McNamara, + * Copyright (C) 2020 Microchip Technology Inc. All rights reserved. + */ + +#ifndef _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ +#define _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ + +#define CLK_CPU 0 +#define CLK_AXI 1 +#define CLK_AHB 2 + +#define CLK_ENVM 3 +#define CLK_MAC0 4 +#define CLK_MAC1 5 +#define CLK_MMC 6 +#define CLK_TIMER 7 +#define CLK_MMUART0 8 +#define CLK_MMUART1 9 +#define CLK_MMUART2 10 +#define CLK_MMUART3 11 +#define CLK_MMUART4 12 +#define CLK_SPI0 13 +#define CLK_SPI1 14 +#define CLK_I2C0 15 +#define CLK_I2C1 16 +#define CLK_CAN0 17 +#define CLK_CAN1 18 +#define CLK_USB 19 +#define CLK_RESERVED 20 +#define CLK_RTC 21 +#define CLK_QSPI 22 +#define CLK_GPIO0 23 +#define CLK_GPIO1 24 +#define CLK_GPIO2 25 +#define CLK_DDRC 26 +#define CLK_FIC0 27 +#define CLK_FIC1 28 +#define CLK_FIC2 29 +#define CLK_FIC3 30 +#define CLK_ATHENA 31 +#define CLK_CFM 32 + +#endif /* _DT_BINDINGS_CLK_MICROCHIP_MPFS_H_ */ -- 2.33.1