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Fri, 10 Dec 2021 03:37:27 -0800 (PST) Received: from thinkpad ([202.21.42.75]) by smtp.gmail.com with ESMTPSA id kk7sm14517702pjb.19.2021.12.10.03.37.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 10 Dec 2021 03:37:27 -0800 (PST) Date: Fri, 10 Dec 2021 17:07:20 +0530 From: Manivannan Sadhasivam To: Dmitry Baryshkov Cc: Andy Gross , Bjorn Andersson , Rob Herring , Vinod Koul , Kishon Vijay Abraham I , Stanimir Varbanov , Lorenzo Pieralisi , Bjorn Helgaas , Krzysztof =?utf-8?Q?Wilczy=C5=84ski?= , linux-arm-msm@vger.kernel.org, linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-phy@lists.infradead.org Subject: Re: [PATCH v2 07/10] arm64: dts: qcom: sm8450: add PCIe0 PHY node Message-ID: <20211210113720.GG1734@thinkpad> References: <20211208171442.1327689-1-dmitry.baryshkov@linaro.org> <20211208171442.1327689-8-dmitry.baryshkov@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20211208171442.1327689-8-dmitry.baryshkov@linaro.org> Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org On Wed, Dec 08, 2021 at 08:14:39PM +0300, Dmitry Baryshkov wrote: > Add device tree node for the first PCIe PHY device found on the Qualcomm > SM8450 platform. > > Signed-off-by: Dmitry Baryshkov > --- > arch/arm64/boot/dts/qcom/sm8450.dtsi | 42 ++++++++++++++++++++++++++-- > 1 file changed, 40 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/sm8450.dtsi b/arch/arm64/boot/dts/qcom/sm8450.dtsi > index 16a789cacb65..a047d8a22897 100644 > --- a/arch/arm64/boot/dts/qcom/sm8450.dtsi > +++ b/arch/arm64/boot/dts/qcom/sm8450.dtsi > @@ -558,8 +558,12 @@ gcc: clock-controller@100000 { > #clock-cells = <1>; > #reset-cells = <1>; > #power-domain-cells = <1>; > - clock-names = "bi_tcxo", "sleep_clk"; > - clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>; > + clocks = <&rpmhcc RPMH_CXO_CLK>, > + <&pcie0_lane>, > + <&sleep_clk>; > + clock-names = "bi_tcxo", > + "pcie_0_pipe_clk", > + "sleep_clk"; > }; > > qupv3_id_0: geniqup@9c0000 { > @@ -625,6 +629,40 @@ i2c14: i2c@a98000 { > }; > }; > > + pcie0_phy: phy@1c06000 { > + compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy"; > + reg = <0 0x01c06000 0 0x200>; > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + clocks = <&gcc GCC_PCIE_0_AUX_CLK>, > + <&gcc GCC_PCIE_0_CFG_AHB_CLK>, > + <&gcc GCC_PCIE_0_CLKREF_EN>, > + <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; > + clock-names = "aux", "cfg_ahb", "ref", "refgen"; > + > + resets = <&gcc GCC_PCIE_0_PHY_BCR>; > + reset-names = "phy"; > + > + assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; > + assigned-clock-rates = <100000000>; > + > + status = "disabled"; > + > + pcie0_lane: lanes@1c06200 { > + reg = <0 0x1c06e00 0 0x200>, /* tx */ > + <0 0x1c07000 0 0x200>, /* rx */ > + <0 0x1c06200 0 0x200>, /* pcs */ Oh, so this platform has "PCS" at the starting offset? This is different compared to other platforms as "TX" always comes first. And the size is "0x200" for all? Thanks, Mani > + <0 0x1c06600 0 0x200>; /* pcs_pcie */ > + clocks = <&gcc GCC_PCIE_0_PIPE_CLK>; > + clock-names = "pipe0"; > + > + #clock-cells = <0>; > + #phy-cells = <0>; > + clock-output-names = "pcie_0_pipe_clk"; > + }; > + }; > + > config_noc: interconnect@1500000 { > compatible = "qcom,sm8450-config-noc"; > reg = <0 0x01500000 0 0x1c000>; > -- > 2.33.0 >