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From: Pratyush Yadav <p.yadav@ti.com>
To: Dinh Nguyen <dinguyen@kernel.org>
Cc: Dinh Nguyen <dinh.linux@gmail.com>, <devicetree@vger.kernel.org>,
	<broonie@kernel.org>, <robh+dt@kernel.org>
Subject: Re: [PATCHv2 1/3] dt-bindings: spi: cadence-quadspi: document "cdns,qspi-nor-ver-00-10"
Date: Fri, 17 Dec 2021 00:28:16 +0530	[thread overview]
Message-ID: <20211216185814.xmljmryvghdtojnj@ti.com> (raw)
In-Reply-To: <ad4bbd06-ef56-895c-f30c-4897420843c7@kernel.org>

On 15/12/21 09:36AM, Dinh Nguyen wrote:
> 
> 
> On 12/14/21 2:05 PM, Pratyush Yadav wrote:
> > On 08/12/21 05:45PM, Dinh Nguyen wrote:
> > > On Mon, Dec 6, 2021 at 9:51 PM Pratyush Yadav <p.yadav@ti.com> wrote:
> > > > 
> > > > On 03/12/21 12:17PM, Dinh Nguyen wrote:
> > > > > The QSPI controller on Intel's SoCFPGA platform does not implement the
> > > > > CQSPI_REG_WR_COMPLETION_CTRL register, thus a write to this register
> > > > > results in a crash.
> > > > > 
> > > > > The module/revision ID is written in the MODULE_ID register. For this
> > > > > variance, bits 23-8 is 0x0010.
> > > > 
> > > > When I looked at your original patches I was under the impression that
> > > > this was a SoCFPGA specific thing and did not apply to other
> > > > implementation of the IP in general.
> > > > 
> > > > If this is indeed a generic thing and we can detect it via the MODULE_ID
> > > > register [0], then why not just read that register at probe time and
> > > > apply this quirk based on the ID? Why then do we need a separate
> > > > compatible at all?
> > > > 
> > > > [0] I would like to see it stated explicitly somewhere that version
> > > > 0x0010 does not support the WR_COMPLETION_CTRL register.
> > > > 
> > > 
> > > I cannot for sure confirm that this condition applies to only 0x0010
> > > version of the
> > > IP. I can verify that the IP that is in all 3 generations of SoCFPGA
> > > devices, all have
> > > MODULE_ID value of 0x0010 and all do not have the WR_COMPLETION_CTRL
> > > register implemented.
> > 
> > I agree with Rob here. If you are not sure that this is a generic IP
> > thing then you should not use a generic compatible.
> > 
> 
> 
> I think using the binding of "intel,socfpga-qspi" should be fine? If we go
> by the MODULE_ID value as a indicator of versions, then the version hasn't
> changed for all revisions of the SoCFPGA, dating back to the original
> Cyclone5, which was introduced in 2012.

Yes, I think you should keep using the SoC specific binding unless you 
can find some documentation from Cadence that says all parts with this 
MODULE_ID value don't have the WR_COMPLETION_CTRL register.

-- 
Regards,
Pratyush Yadav
Texas Instruments Inc.

  reply	other threads:[~2021-12-16 18:58 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-12-03 18:17 [PATCHv2 1/3] dt-bindings: spi: cadence-quadspi: document "cdns,qspi-nor-ver-00-10" Dinh Nguyen
2021-12-03 18:17 ` [PATCHv2 2/3] ARM: dts: socfpga: change qspi to "cdns,qspi-nor-ver-00-10" Dinh Nguyen
2021-12-03 18:17 ` [PATCH 3/3] spi: cadence-quadspi: change socfpga-qspi " Dinh Nguyen
2021-12-03 18:18 ` [PATCHv2 1/3] dt-bindings: spi: cadence-quadspi: document "cdns,qspi-nor-ver-00-10" Mark Brown
2021-12-03 19:05   ` Dinh Nguyen
2021-12-06 10:22 ` Pratyush Yadav
2021-12-08 23:45   ` Dinh Nguyen
2021-12-13 20:48     ` Rob Herring
2021-12-13 21:21       ` Dinh Nguyen
2021-12-14 20:05     ` Pratyush Yadav
2021-12-15 15:36       ` Dinh Nguyen
2021-12-16 18:58         ` Pratyush Yadav [this message]
  -- strict thread matches above, loose matches on Subject: below --
2021-12-03 17:32 Dinh Nguyen
2021-12-03 14:01 Dinh Nguyen

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