From: Ansuel Smith <ansuelsmth@gmail.com>
To: Andy Gross <agross@kernel.org>,
Bjorn Andersson <bjorn.andersson@linaro.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Ansuel Smith <ansuelsmth@gmail.com>,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH 04/14] drivers: clk: qcom: gcc-ipq806x: use ARRAY_SIZE for num_parents
Date: Tue, 18 Jan 2022 01:44:24 +0100 [thread overview]
Message-ID: <20220118004434.17095-5-ansuelsmth@gmail.com> (raw)
In-Reply-To: <20220118004434.17095-1-ansuelsmth@gmail.com>
Use ARRAY_SIZE for num_parents instead of hardcoding the value.
Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
---
drivers/clk/qcom/gcc-ipq806x.c | 68 +++++++++++++++++-----------------
1 file changed, 34 insertions(+), 34 deletions(-)
diff --git a/drivers/clk/qcom/gcc-ipq806x.c b/drivers/clk/qcom/gcc-ipq806x.c
index cbacd56f52d4..17ce61f36b08 100644
--- a/drivers/clk/qcom/gcc-ipq806x.c
+++ b/drivers/clk/qcom/gcc-ipq806x.c
@@ -385,7 +385,7 @@ static struct clk_rcg gsbi1_uart_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi1_uart_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -436,7 +436,7 @@ static struct clk_rcg gsbi2_uart_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi2_uart_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -487,7 +487,7 @@ static struct clk_rcg gsbi4_uart_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi4_uart_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -538,7 +538,7 @@ static struct clk_rcg gsbi5_uart_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi5_uart_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -589,7 +589,7 @@ static struct clk_rcg gsbi6_uart_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi6_uart_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -640,7 +640,7 @@ static struct clk_rcg gsbi7_uart_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi7_uart_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -704,7 +704,7 @@ static struct clk_rcg gsbi1_qup_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi1_qup_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -755,7 +755,7 @@ static struct clk_rcg gsbi2_qup_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi2_qup_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -806,7 +806,7 @@ static struct clk_rcg gsbi4_qup_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi4_qup_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -857,7 +857,7 @@ static struct clk_rcg gsbi5_qup_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi5_qup_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -908,7 +908,7 @@ static struct clk_rcg gsbi6_qup_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi6_qup_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -959,7 +959,7 @@ static struct clk_rcg gsbi7_qup_src = {
.hw.init = &(struct clk_init_data){
.name = "gsbi7_qup_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -1111,7 +1111,7 @@ static struct clk_rcg gp0_src = {
.hw.init = &(struct clk_init_data){
.name = "gp0_src",
.parent_data = gcc_pxo_pll8_cxo,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
.ops = &clk_rcg_ops,
.flags = CLK_SET_PARENT_GATE,
},
@@ -1162,7 +1162,7 @@ static struct clk_rcg gp1_src = {
.hw.init = &(struct clk_init_data){
.name = "gp1_src",
.parent_data = gcc_pxo_pll8_cxo,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -1213,7 +1213,7 @@ static struct clk_rcg gp2_src = {
.hw.init = &(struct clk_init_data){
.name = "gp2_src",
.parent_data = gcc_pxo_pll8_cxo,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_cxo),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -1269,7 +1269,7 @@ static struct clk_rcg prng_src = {
.hw.init = &(struct clk_init_data){
.name = "prng_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
},
@@ -1333,7 +1333,7 @@ static struct clk_rcg sdc1_src = {
.hw.init = &(struct clk_init_data){
.name = "sdc1_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
}
@@ -1383,7 +1383,7 @@ static struct clk_rcg sdc3_src = {
.hw.init = &(struct clk_init_data){
.name = "sdc3_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
}
@@ -1468,7 +1468,7 @@ static struct clk_rcg tsif_ref_src = {
.hw.init = &(struct clk_init_data){
.name = "tsif_ref_src",
.parent_data = gcc_pxo_pll8,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8),
.ops = &clk_rcg_ops,
},
}
@@ -1632,7 +1632,7 @@ static struct clk_rcg pcie_ref_src = {
.hw.init = &(struct clk_init_data){
.name = "pcie_ref_src",
.parent_data = gcc_pxo_pll3,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll3),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -1726,7 +1726,7 @@ static struct clk_rcg pcie1_ref_src = {
.hw.init = &(struct clk_init_data){
.name = "pcie1_ref_src",
.parent_data = gcc_pxo_pll3,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll3),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -1820,7 +1820,7 @@ static struct clk_rcg pcie2_ref_src = {
.hw.init = &(struct clk_init_data){
.name = "pcie2_ref_src",
.parent_data = gcc_pxo_pll3,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll3),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -1919,7 +1919,7 @@ static struct clk_rcg sata_ref_src = {
.hw.init = &(struct clk_init_data){
.name = "sata_ref_src",
.parent_data = gcc_pxo_pll3,
- .num_parents = 2,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll3),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -2062,7 +2062,7 @@ static struct clk_rcg usb30_master_clk_src = {
.hw.init = &(struct clk_init_data){
.name = "usb30_master_ref_src",
.parent_data = gcc_pxo_pll8_pll0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -2136,7 +2136,7 @@ static struct clk_rcg usb30_utmi_clk = {
.hw.init = &(struct clk_init_data){
.name = "usb30_utmi_clk",
.parent_data = gcc_pxo_pll8_pll0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -2210,7 +2210,7 @@ static struct clk_rcg usb_hs1_xcvr_clk_src = {
.hw.init = &(struct clk_init_data){
.name = "usb_hs1_xcvr_src",
.parent_data = gcc_pxo_pll8_pll0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -2276,7 +2276,7 @@ static struct clk_rcg usb_fs1_xcvr_clk_src = {
.hw.init = &(struct clk_init_data){
.name = "usb_fs1_xcvr_src",
.parent_data = gcc_pxo_pll8_pll0,
- .num_parents = 3,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll0),
.ops = &clk_rcg_ops,
.flags = CLK_SET_RATE_GATE,
},
@@ -2412,7 +2412,7 @@ static struct clk_dyn_rcg gmac_core1_src = {
.hw.init = &(struct clk_init_data){
.name = "gmac_core1_src",
.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
.ops = &clk_dyn_rcg_ops,
},
},
@@ -2484,7 +2484,7 @@ static struct clk_dyn_rcg gmac_core2_src = {
.hw.init = &(struct clk_init_data){
.name = "gmac_core2_src",
.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
.ops = &clk_dyn_rcg_ops,
},
},
@@ -2556,7 +2556,7 @@ static struct clk_dyn_rcg gmac_core3_src = {
.hw.init = &(struct clk_init_data){
.name = "gmac_core3_src",
.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
.ops = &clk_dyn_rcg_ops,
},
},
@@ -2628,7 +2628,7 @@ static struct clk_dyn_rcg gmac_core4_src = {
.hw.init = &(struct clk_init_data){
.name = "gmac_core4_src",
.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
.ops = &clk_dyn_rcg_ops,
},
},
@@ -2688,7 +2688,7 @@ static struct clk_dyn_rcg nss_tcm_src = {
.hw.init = &(struct clk_init_data){
.name = "nss_tcm_src",
.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
.ops = &clk_dyn_rcg_ops,
},
},
@@ -2766,7 +2766,7 @@ static struct clk_dyn_rcg ubi32_core1_src_clk = {
.hw.init = &(struct clk_init_data){
.name = "ubi32_core1_src_clk",
.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
.ops = &clk_dyn_rcg_ops,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
},
@@ -2819,7 +2819,7 @@ static struct clk_dyn_rcg ubi32_core2_src_clk = {
.hw.init = &(struct clk_init_data){
.name = "ubi32_core2_src_clk",
.parent_data = gcc_pxo_pll8_pll14_pll18_pll0,
- .num_parents = 5,
+ .num_parents = ARRAY_SIZE(gcc_pxo_pll8_pll14_pll18_pll0),
.ops = &clk_dyn_rcg_ops,
.flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
},
--
2.33.1
next prev parent reply other threads:[~2022-01-18 1:02 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-18 0:44 [PATCH 00/14] Multiple addition and improvement to ipq8064 gcc Ansuel Smith
2022-01-18 0:44 ` [PATCH 01/14] dt-bindings: clock: Document qcom,gcc-ipq8064 binding Ansuel Smith
2022-01-18 1:32 ` Rob Herring
2022-01-19 13:59 ` Rob Herring
2022-01-19 14:10 ` Ansuel Smith
2022-01-18 0:44 ` [PATCH 02/14] drivers: clk: qcom: gcc-ipq806x: fix wrong naming for gcc_pxo_pll8_pll0 Ansuel Smith
2022-01-18 0:44 ` [PATCH 03/14] drivers: clk: qcom: gcc-ipq806x: convert parent_names to parent_data Ansuel Smith
2022-01-18 18:41 ` Marijn Suijten
2022-01-18 18:44 ` Ansuel Smith
2022-01-18 0:44 ` Ansuel Smith [this message]
2022-01-18 0:44 ` [PATCH 05/14] drivers: clk: qcom: gcc-ipq806x: drop hardcoded pxo and cxo source clk Ansuel Smith
2022-01-18 0:44 ` [PATCH 06/14] drivers: clk: qcom: gcc-ipq806x: use parent_hws where possible Ansuel Smith
2022-01-18 0:44 ` [PATCH 07/14] drivers: clk: qcom: gcc-ipq806x: add additional freq nss cores Ansuel Smith
2022-01-18 0:44 ` [PATCH 08/14] drivers: clk: qcom: gcc-ipq806x: add unusued flag for critical clock Ansuel Smith
2022-01-18 0:44 ` [PATCH 09/14] drivers: clk: qcom: gcc-ipq806x: add additional freq for sdc table Ansuel Smith
2022-01-18 0:44 ` [PATCH 10/14] dt-bindings: clock: add ipq8064 ce5 clk define Ansuel Smith
2022-01-18 0:44 ` [PATCH 11/14] drivers: clk: qcom: gcc-ipq806x: add CryptoEngine clocks Ansuel Smith
2022-01-18 0:44 ` [PATCH 12/14] dt-bindings: reset: add ipq8064 ce5 resets Ansuel Smith
2022-01-18 0:44 ` [PATCH 13/14] drivers: clk: qcom: gcc-ipq806x: add CryptoEngine resets Ansuel Smith
2022-01-18 0:44 ` [PATCH 14/14] ARM: dts: qcom: Add syscon and cxo/pxo clock to gcc node for ipq8064 Ansuel Smith
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