[PATCH 0/2] J721S2: Add support for PCIE

[PATCH 0/2] J721S2: Add support for PCIE

[Aswath Govindraju]

The following series of patches add support for single
instance of PCIe brought out on J721S2 common processor
board.

Notes:
- Applying this patch series **breaks the boot** of J721S2.
  This is because of the following commit,
  "19e863828acf PCI: j721e: Drop redundant struct device *"
  Dicussions are currently ongoing regarding the required
  fix.

- This needs to be merged after the following patch
  to avoid dtbs_check errors
  https://lkml.org/lkml/2021/11/29/1752

Aswath Govindraju (2):
  arm64: dts: ti: k3-j721s2-main: Add PCIe device tree node
  arm64: dts: ti: k3-j721s2-common-proc-board: Enable PCIe

 .../dts/ti/k3-j721s2-common-proc-board.dts    | 14 ++++++
 arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi    | 48 +++++++++++++++++++
 2 files changed, 62 insertions(+)

-- 
2.17.1

[PATCH 1/2] arm64: dts: ti: k3-j721s2-main: Add PCIe device tree node

[Aswath Govindraju]

Add PCIe device tree node (both RC and EP) for the single PCIe
instance present in j721s2.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
---
 arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 48 ++++++++++++++++++++++
 1 file changed, 48 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
index ebd55032e59c..dc365a1880d0 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
@@ -795,6 +795,54 @@
 		};
 	};
 
+	pcie1_rc: pcie@2910000 {
+		compatible = "ti,j7200-pcie-host", "ti,j721e-pcie-host";
+		reg = <0x00 0x02910000 0x00 0x1000>,
+		      <0x00 0x02917000 0x00 0x400>,
+		      <0x00 0x0d800000 0x00 0x00800000>,
+		      <0x00 0x18000000 0x00 0x00001000>;
+		reg-names = "intd_cfg", "user_cfg", "reg", "cfg";
+		interrupt-names = "link_state";
+		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
+		device_type = "pci";
+		ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
+		max-link-speed = <3>;
+		num-lanes = <4>;
+		power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 276 41>;
+		clock-names = "fck";
+		#address-cells = <3>;
+		#size-cells = <2>;
+		bus-range = <0x0 0xff>;
+		vendor-id = <0x104c>;
+		device-id = <0xb013>;
+		msi-map = <0x0 &gic_its 0x0 0x10000>;
+		dma-coherent;
+		ranges = <0x01000000 0x0 0x18001000  0x00 0x18001000  0x0 0x0010000>,
+			 <0x02000000 0x0 0x18011000  0x00 0x18011000  0x0 0x7fef000>;
+		dma-ranges = <0x02000000 0x0 0x0 0x0 0x0 0x10000 0x0>;
+	};
+
+	pcie1_ep: pcie-ep@2910000 {
+		compatible = "ti,j7200-pcie-ep", "ti,j721e-pcie-ep";
+		reg = <0x00 0x02910000 0x00 0x1000>,
+		      <0x00 0x02917000 0x00 0x400>,
+		      <0x00 0x0d800000 0x00 0x00800000>,
+		      <0x00 0x18000000 0x00 0x08000000>;
+		reg-names = "intd_cfg", "user_cfg", "reg", "mem";
+		interrupt-names = "link_state";
+		interrupts = <GIC_SPI 330 IRQ_TYPE_EDGE_RISING>;
+		ti,syscon-pcie-ctrl = <&scm_conf 0x074>;
+		max-link-speed = <3>;
+		num-lanes = <4>;
+		power-domains = <&k3_pds 276 TI_SCI_PD_EXCLUSIVE>;
+		clocks = <&k3_clks 276 41>;
+		clock-names = "fck";
+		max-functions = /bits/ 8 <6>;
+		max-virtual-functions = /bits/ 8 <4 4 4 4 0 0>;
+		dma-coherent;
+	};
+
 	main_mcan0: can@2701000 {
 		compatible = "bosch,m_can";
 		reg = <0x00 0x02701000 0x00 0x200>,
-- 
2.17.1

[PATCH 2/2] arm64: dts: ti: k3-j721s2-common-proc-board: Enable PCIe

[Aswath Govindraju]

x1 lane PCIe slot in the common processor board is enabled and connected to
J721S2 SOM. Add PCIe DT node in common processor board to reflect the
same.

Signed-off-by: Aswath Govindraju <a-govindraju@ti.com>
---
 .../boot/dts/ti/k3-j721s2-common-proc-board.dts    | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
index cb99a97af426..793ee77838f4 100644
--- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
+++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts
@@ -428,6 +428,20 @@
 	};
 };
 
+&pcie1_rc {
+	reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>;
+	phys = <&serdes0_pcie_link>;
+	phy-names = "pcie-phy";
+	num-lanes = <1>;
+};
+
+&pcie1_ep {
+	phys = <&serdes0_pcie_link>;
+	phy-names = "pcie-phy";
+	num-lanes = <1>;
+	status = "disabled";
+};
+
 &mcu_mcan0 {
 	pinctrl-names = "default";
 	pinctrl-0 = <&mcu_mcan0_pins_default>;
-- 
2.17.1

Re: [PATCH 0/2] J721S2: Add support for PCIE

[Nishanth Menon]

On 18:42-20220125, Aswath Govindraju wrote:
> The following series of patches add support for single
> instance of PCIe brought out on J721S2 common processor
> board.
> 
> Notes:
> - Applying this patch series **breaks the boot** of J721S2.
>   This is because of the following commit,
>   "19e863828acf PCI: j721e: Drop redundant struct device *"
>   Dicussions are currently ongoing regarding the required
>   fix.
> 
> - This needs to be merged after the following patch
>   to avoid dtbs_check errors
>   https://lkml.org/lkml/2021/11/29/1752

Lets pick this up in 5.18-rc1 window then for 5.19
(assuming this will make it to master by 5.18-rc1)

> 
> Aswath Govindraju (2):
>   arm64: dts: ti: k3-j721s2-main: Add PCIe device tree node
>   arm64: dts: ti: k3-j721s2-common-proc-board: Enable PCIe
> 
>  .../dts/ti/k3-j721s2-common-proc-board.dts    | 14 ++++++
>  arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi    | 48 +++++++++++++++++++
>  2 files changed, 62 insertions(+)

Also, please notice the following in MAINTAINER file and make sure lakml
is in cc next time.
 L:      linux-arm-kernel@lists.infradead.org (moderated for non-subscribers)

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D