From: Robert Hancock <robert.hancock@calian.com>
To: linux-usb@vger.kernel.org
Cc: balbi@kernel.org, gregkh@linuxfoundation.org,
michal.simek@xilinx.com, manish.narani@xilinx.com,
sean.anderson@seco.com, robh+dt@kernel.org,
devicetree@vger.kernel.org, piyush.mehta@xilinx.com,
Robert Hancock <robert.hancock@calian.com>
Subject: [PATCH v8 3/3] usb: dwc3: xilinx: Add ULPI PHY reset handling
Date: Wed, 26 Jan 2022 17:40:17 -0600 [thread overview]
Message-ID: <20220126234017.3619108-4-robert.hancock@calian.com> (raw)
In-Reply-To: <20220126234017.3619108-1-robert.hancock@calian.com>
Hook up an optional GPIO-based reset for the connected USB ULPI PHY
device. This is typically already done by the first-stage boot loader,
however it can be more robust to ensure this reset is done prior to
loading the driver in Linux.
Based on a patch "usb: dwc3: xilinx: Add gpio-reset support" in the
Xilinx kernel tree by Piyush Mehta <piyush.mehta@xilinx.com>.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
---
drivers/usb/dwc3/dwc3-xilinx.c | 19 +++++++++++++++++++
1 file changed, 19 insertions(+)
diff --git a/drivers/usb/dwc3/dwc3-xilinx.c b/drivers/usb/dwc3/dwc3-xilinx.c
index a6f3a9b38789..1ee6011ada44 100644
--- a/drivers/usb/dwc3/dwc3-xilinx.c
+++ b/drivers/usb/dwc3/dwc3-xilinx.c
@@ -11,6 +11,7 @@
#include <linux/slab.h>
#include <linux/clk.h>
#include <linux/of.h>
+#include <linux/gpio/consumer.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <linux/of_platform.h>
@@ -101,6 +102,7 @@ static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *priv_data)
struct phy *usb3_phy;
int ret = 0;
u32 reg;
+ struct gpio_desc *reset_gpio;
usb3_phy = devm_phy_optional_get(dev, "usb3-phy");
if (IS_ERR(usb3_phy)) {
@@ -110,6 +112,14 @@ static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *priv_data)
goto err;
}
+ reset_gpio = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH);
+ if (IS_ERR(reset_gpio)) {
+ ret = PTR_ERR(reset_gpio);
+ dev_err_probe(dev, ret,
+ "Failed to get reset gpio\n");
+ goto err;
+ }
+
/*
* The following core resets are not required unless a USB3 PHY
* is used, and the subsequent register settings are not required
@@ -201,6 +211,15 @@ static int dwc3_xlnx_init_zynqmp(struct dwc3_xlnx *priv_data)
}
skip_usb3_phy:
+ /* ulpi reset via gpio-modepin or gpio-framework driver */
+ if (reset_gpio) {
+ /* Toggle ulpi to reset the phy. */
+ gpiod_set_value(reset_gpio, 0);
+ usleep_range(5000, 10000); /* delay */
+ gpiod_set_value(reset_gpio, 1);
+ usleep_range(5000, 10000); /* delay */
+ }
+
/*
* This routes the USB DMA traffic to go through FPD path instead
* of reaching DDR directly. This traffic routing is needed to
--
2.31.1
next prev parent reply other threads:[~2022-01-26 23:40 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-01-26 23:40 [PATCH v8 0/3] Xilinx ZynqMP USB fixes Robert Hancock
2022-01-26 23:40 ` [PATCH v8 1/3] usb: dwc3: xilinx: fix uninitialized return value Robert Hancock
2022-01-26 23:40 ` [PATCH v8 2/3] dt-bindings: usb: dwc3-xilinx: Added reset-gpios Robert Hancock
2022-02-02 0:58 ` Rob Herring
2022-01-26 23:40 ` Robert Hancock [this message]
2022-01-27 20:10 ` [PATCH v8 3/3] usb: dwc3: xilinx: Add ULPI PHY reset handling Sean Anderson
2022-01-27 21:45 ` Robert Hancock
2022-02-09 16:56 ` Piyush Mehta
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