* [PATCH V7 0/2] Add thead,c900-plic support @ 2022-01-30 13:56 guoren 2022-01-30 13:56 ` [PATCH V7 1/2] dt-bindings: update riscv plic compatible string guoren 2022-01-30 13:56 ` [PATCH V7 2/2] irqchip/sifive-plic: Fixup thead,c900-plic DT parse missing guoren 0 siblings, 2 replies; 6+ messages in thread From: guoren @ 2022-01-30 13:56 UTC (permalink / raw) To: guoren, anup, maz, tglx, palmer, samuel Cc: linux-kernel, linux-riscv, devicetree, Guo Ren From: Guo Ren <guoren@linux.alibaba.com> Add the compatible string "thead,c900-plic" to the riscv plic bindings to support allwinner d1 SOC which contains c906 core. Changes since V7: - Remove /proc/interrupts display part modification Changes since V6: - Modify sifive,plic-1.0.0.yaml comment - Remove vendor-prefixes patch which has been merged - Only put dt naming distinguish in sifive-plic.c Changes since V5: - Move back to mask/unmask - Fixup the problem in eoi callback - Remove allwinner,sun20i-d1 IRQCHIP_DECLARE - Rewrite comment log - Add DT list - Fixup compatible string - Remove allwinner-d1 compatible - make dt_binding_check - Add T-head vendor-prefixes Changes since V4: - Update description in errata style - Update enum suggested by Anup, Heiko, Samuel - Update comment by Anup - Add cover-letter Changes since V3: - Rename "c9xx" to "c900" - Add thead,c900-plic in the description section - Add sifive_plic_chip and thead_plic_chip for difference Changes since V2: - Add a separate compatible string "thead,c9xx-plic" - set irq_mask/unmask of "plic_chip" to NULL and point irq_enable/disable of "plic_chip" to plic_irq_mask/unmask - Add a detailed comment block in plic_init() about the differences in Claim/Completion process of RISC-V PLIC and C9xx PLIC. Guo Ren (2): dt-bindings: update riscv plic compatible string irqchip/sifive-plic: Fixup thead,c900-plic DT parse missing .../sifive,plic-1.0.0.yaml | 21 +++++++++++++------ drivers/irqchip/irq-sifive-plic.c | 1 + 2 files changed, 16 insertions(+), 6 deletions(-) -- 2.25.1 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH V7 1/2] dt-bindings: update riscv plic compatible string 2022-01-30 13:56 [PATCH V7 0/2] Add thead,c900-plic support guoren @ 2022-01-30 13:56 ` guoren 2022-02-02 1:00 ` Rob Herring 2022-01-30 13:56 ` [PATCH V7 2/2] irqchip/sifive-plic: Fixup thead,c900-plic DT parse missing guoren 1 sibling, 1 reply; 6+ messages in thread From: guoren @ 2022-01-30 13:56 UTC (permalink / raw) To: guoren, anup, maz, tglx, palmer, samuel Cc: linux-kernel, linux-riscv, devicetree, Guo Ren, Heiko Stuebner, Rob Herring, Rob Herring From: Guo Ren <guoren@linux.alibaba.com> Add the compatible string "thead,c900-plic" to the riscv plic bindings to support allwinner d1 SOC which contains c906 core. Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Cc: Anup Patel <anup@brainfault.org> Cc: Heiko Stuebner <heiko@sntech.de> Cc: Rob Herring <robh@kernel.org> Cc: Rob Herring <robh+dt@kernel.org> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Samuel Holland <samuel@sholland.org> --- .../sifive,plic-1.0.0.yaml | 21 +++++++++++++------ 1 file changed, 15 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index 28b6b17fe4b2..1fa5aa7e4c2e 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -35,6 +35,10 @@ description: contains a specific memory layout, which is documented in chapter 8 of the SiFive U5 Coreplex Series Manual <https://static.dev.sifive.com/U54-MC-RVCoreIP.pdf>. + The thead,c900-plic is different from sifive,plic-1.0.0 in opensbi, the + T-HEAD PLIC implementation requires setting a delegation bit to allow access + from S-mode. So add thead,c900-plic to distinguish them. + maintainers: - Sagar Kadam <sagar.kadam@sifive.com> - Paul Walmsley <paul.walmsley@sifive.com> @@ -42,12 +46,17 @@ maintainers: properties: compatible: - items: - - enum: - - sifive,fu540-c000-plic - - starfive,jh7100-plic - - canaan,k210-plic - - const: sifive,plic-1.0.0 + oneOf: + - items: + - enum: + - sifive,fu540-c000-plic + - starfive,jh7100-plic + - canaan,k210-plic + - const: sifive,plic-1.0.0 + - items: + - enum: + - allwinner,sun20i-d1-plic + - const: thead,c900-plic reg: maxItems: 1 -- 2.25.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH V7 1/2] dt-bindings: update riscv plic compatible string 2022-01-30 13:56 ` [PATCH V7 1/2] dt-bindings: update riscv plic compatible string guoren @ 2022-02-02 1:00 ` Rob Herring 0 siblings, 0 replies; 6+ messages in thread From: Rob Herring @ 2022-02-02 1:00 UTC (permalink / raw) To: guoren Cc: anup, Guo Ren, devicetree, linux-riscv, Heiko Stuebner, linux-kernel, maz, tglx, Rob Herring, palmer, samuel On Sun, 30 Jan 2022 21:56:33 +0800, guoren@kernel.org wrote: > From: Guo Ren <guoren@linux.alibaba.com> > > Add the compatible string "thead,c900-plic" to the riscv plic > bindings to support allwinner d1 SOC which contains c906 core. > > Signed-off-by: Guo Ren <guoren@linux.alibaba.com> > Cc: Anup Patel <anup@brainfault.org> > Cc: Heiko Stuebner <heiko@sntech.de> > Cc: Rob Herring <robh@kernel.org> > Cc: Rob Herring <robh+dt@kernel.org> > Cc: Palmer Dabbelt <palmer@dabbelt.com> > Cc: Samuel Holland <samuel@sholland.org> > --- > .../sifive,plic-1.0.0.yaml | 21 +++++++++++++------ > 1 file changed, 15 insertions(+), 6 deletions(-) > Reviewed-by: Rob Herring <robh@kernel.org> ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH V7 2/2] irqchip/sifive-plic: Fixup thead,c900-plic DT parse missing 2022-01-30 13:56 [PATCH V7 0/2] Add thead,c900-plic support guoren 2022-01-30 13:56 ` [PATCH V7 1/2] dt-bindings: update riscv plic compatible string guoren @ 2022-01-30 13:56 ` guoren 2022-02-02 4:42 ` Samuel Holland 1 sibling, 1 reply; 6+ messages in thread From: guoren @ 2022-01-30 13:56 UTC (permalink / raw) To: guoren, anup, maz, tglx, palmer, samuel Cc: linux-kernel, linux-riscv, devicetree, Guo Ren From: Guo Ren <guoren@linux.alibaba.com> The thead,c900-plic has been used in opensbi to distinguish PLIC [1]. Although PLICs have the same behaviors in Linux, they are different hardware with some custom initializing in firmware(opensbi). Qute opensbi patch commit-msg by Samuel: The T-HEAD PLIC implementation requires setting a delegation bit to allow access from S-mode. Now that the T-HEAD PLIC has its own compatible string, set this bit automatically from the PLIC driver, instead of reaching into the PLIC's MMIO space from another driver. [1]: https://github.com/riscv-software-src/opensbi/commit/78c2b19218bd62653b9fb31623a42ced45f38ea6 Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Cc: Anup Patel <anup@brainfault.org> Cc: Marc Zyngier <maz@kernel.org> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Samuel Holland <samuel@sholland.org> Cc: Thomas Gleixner <tglx@linutronix.de> --- drivers/irqchip/irq-sifive-plic.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c index 259065d271ef..09cc98266d30 100644 --- a/drivers/irqchip/irq-sifive-plic.c +++ b/drivers/irqchip/irq-sifive-plic.c @@ -398,3 +398,4 @@ static int __init plic_init(struct device_node *node, IRQCHIP_DECLARE(sifive_plic, "sifive,plic-1.0.0", plic_init); IRQCHIP_DECLARE(riscv_plic0, "riscv,plic0", plic_init); /* for legacy systems */ +IRQCHIP_DECLARE(thead_c900_plic, "thead,c900-plic", plic_init); /* for firmware driver */ -- 2.25.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH V7 2/2] irqchip/sifive-plic: Fixup thead,c900-plic DT parse missing 2022-01-30 13:56 ` [PATCH V7 2/2] irqchip/sifive-plic: Fixup thead,c900-plic DT parse missing guoren @ 2022-02-02 4:42 ` Samuel Holland 2022-02-07 9:13 ` Guo Ren 0 siblings, 1 reply; 6+ messages in thread From: Samuel Holland @ 2022-02-02 4:42 UTC (permalink / raw) To: guoren Cc: anup, maz, tglx, palmer, linux-kernel, linux-riscv, devicetree, Guo Ren On 1/30/22 7:56 AM, guoren@kernel.org wrote: > From: Guo Ren <guoren@linux.alibaba.com> > > The thead,c900-plic has been used in opensbi to distinguish > PLIC [1]. Although PLICs have the same behaviors in Linux, > they are different hardware with some custom initializing in > firmware(opensbi). > > Qute opensbi patch commit-msg by Samuel: > > The T-HEAD PLIC implementation requires setting a delegation bit > to allow access from S-mode. Now that the T-HEAD PLIC has its own > compatible string, set this bit automatically from the PLIC driver, > instead of reaching into the PLIC's MMIO space from another driver. > > [1]: https://github.com/riscv-software-src/opensbi/commit/78c2b19218bd62653b9fb31623a42ced45f38ea6 > > Signed-off-by: Guo Ren <guoren@linux.alibaba.com> > Cc: Anup Patel <anup@brainfault.org> > Cc: Marc Zyngier <maz@kernel.org> > Cc: Palmer Dabbelt <palmer@dabbelt.com> > Cc: Samuel Holland <samuel@sholland.org> > Cc: Thomas Gleixner <tglx@linutronix.de> > --- > drivers/irqchip/irq-sifive-plic.c | 1 + > 1 file changed, 1 insertion(+) Tested-by: Samuel Holland <samuel@sholland.org> ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH V7 2/2] irqchip/sifive-plic: Fixup thead,c900-plic DT parse missing 2022-02-02 4:42 ` Samuel Holland @ 2022-02-07 9:13 ` Guo Ren 0 siblings, 0 replies; 6+ messages in thread From: Guo Ren @ 2022-02-07 9:13 UTC (permalink / raw) To: Marc Zyngier Cc: Anup Patel, Thomas Gleixner, Palmer Dabbelt, Linux Kernel Mailing List, linux-riscv, devicetree, Guo Ren, Samuel Holland Hi Marc, On Wed, Feb 2, 2022 at 12:42 PM Samuel Holland <samuel@sholland.org> wrote: > > On 1/30/22 7:56 AM, guoren@kernel.org wrote: > > From: Guo Ren <guoren@linux.alibaba.com> > > > > The thead,c900-plic has been used in opensbi to distinguish > > PLIC [1]. Although PLICs have the same behaviors in Linux, > > they are different hardware with some custom initializing in > > firmware(opensbi). > > > > Qute opensbi patch commit-msg by Samuel: > > > > The T-HEAD PLIC implementation requires setting a delegation bit > > to allow access from S-mode. Now that the T-HEAD PLIC has its own > > compatible string, set this bit automatically from the PLIC driver, > > instead of reaching into the PLIC's MMIO space from another driver. > > > > [1]: https://github.com/riscv-software-src/opensbi/commit/78c2b19218bd62653b9fb31623a42ced45f38ea6 > > > > Signed-off-by: Guo Ren <guoren@linux.alibaba.com> > > Cc: Anup Patel <anup@brainfault.org> > > Cc: Marc Zyngier <maz@kernel.org> > > Cc: Palmer Dabbelt <palmer@dabbelt.com> > > Cc: Samuel Holland <samuel@sholland.org> > > Cc: Thomas Gleixner <tglx@linutronix.de> > > --- > > drivers/irqchip/irq-sifive-plic.c | 1 + > > 1 file changed, 1 insertion(+) > > Tested-by: Samuel Holland <samuel@sholland.org> ping... gently. Any problem with the above patch? -- Best Regards Guo Ren ML: https://lore.kernel.org/linux-csky/ ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-02-07 9:19 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-01-30 13:56 [PATCH V7 0/2] Add thead,c900-plic support guoren 2022-01-30 13:56 ` [PATCH V7 1/2] dt-bindings: update riscv plic compatible string guoren 2022-02-02 1:00 ` Rob Herring 2022-01-30 13:56 ` [PATCH V7 2/2] irqchip/sifive-plic: Fixup thead,c900-plic DT parse missing guoren 2022-02-02 4:42 ` Samuel Holland 2022-02-07 9:13 ` Guo Ren
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