* [PATCH v2 2/4] dt-bindings: mmc: sunxi: Add Allwinner F1c100s compatibles
2022-01-30 22:03 [PATCH v2 1/4] ARM: dtsi: suniv: F1c100s add clock and reset macros Jesse Taube
@ 2022-01-30 22:03 ` Jesse Taube
2022-01-31 9:45 ` Maxime Ripard
` (2 more replies)
2022-01-30 22:03 ` [PATCH v2 3/4] ARM: dtsi: suniv: Add mmc to f1c100s dtsi Jesse Taube
` (2 subsequent siblings)
3 siblings, 3 replies; 12+ messages in thread
From: Jesse Taube @ 2022-01-30 22:03 UTC (permalink / raw)
To: devicetree
Cc: robh+dt, Mr.Bossman075, andre.przywara, linux-sunxi, mripard,
linux-arm-kernel
Add binding for F1c100s's mmc controller.
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
---
V1 -> V2:
* New commit
---
.../devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml b/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml
index 4f62ad6ce50c..76137132500d 100644
--- a/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml
+++ b/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml
@@ -55,6 +55,9 @@ properties:
- items:
- const: allwinner,sun50i-h616-mmc
- const: allwinner,sun50i-a100-mmc
+ - items:
+ - const: allwinner,suniv-f1c100s-mmc
+ - const: allwinner,sun7i-a20-mmc
reg:
maxItems: 1
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v2 2/4] dt-bindings: mmc: sunxi: Add Allwinner F1c100s compatibles
2022-01-30 22:03 ` [PATCH v2 2/4] dt-bindings: mmc: sunxi: Add Allwinner F1c100s compatibles Jesse Taube
@ 2022-01-31 9:45 ` Maxime Ripard
2022-01-31 10:19 ` Andre Przywara
2022-02-09 21:15 ` Rob Herring
2 siblings, 0 replies; 12+ messages in thread
From: Maxime Ripard @ 2022-01-31 9:45 UTC (permalink / raw)
To: Jesse Taube
Cc: devicetree, robh+dt, andre.przywara, linux-sunxi,
linux-arm-kernel
[-- Attachment #1: Type: text/plain, Size: 281 bytes --]
Hi,
On Sun, Jan 30, 2022 at 05:03:23PM -0500, Jesse Taube wrote:
> Add binding for F1c100s's mmc controller.
>
> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Some description of why the A20 is a good pick compared to the other
variants would be nice.
Maxime
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^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 2/4] dt-bindings: mmc: sunxi: Add Allwinner F1c100s compatibles
2022-01-30 22:03 ` [PATCH v2 2/4] dt-bindings: mmc: sunxi: Add Allwinner F1c100s compatibles Jesse Taube
2022-01-31 9:45 ` Maxime Ripard
@ 2022-01-31 10:19 ` Andre Przywara
2022-02-09 21:15 ` Rob Herring
2 siblings, 0 replies; 12+ messages in thread
From: Andre Przywara @ 2022-01-31 10:19 UTC (permalink / raw)
To: Jesse Taube; +Cc: devicetree, robh+dt, linux-sunxi, mripard, linux-arm-kernel
On Sun, 30 Jan 2022 17:03:23 -0500
Jesse Taube <mr.bossman075@gmail.com> wrote:
> Add binding for F1c100s's mmc controller.
>
> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Cheers,
Andre
> ---
> V1 -> V2:
> * New commit
> ---
> .../devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml b/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml
> index 4f62ad6ce50c..76137132500d 100644
> --- a/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml
> +++ b/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml
> @@ -55,6 +55,9 @@ properties:
> - items:
> - const: allwinner,sun50i-h616-mmc
> - const: allwinner,sun50i-a100-mmc
> + - items:
> + - const: allwinner,suniv-f1c100s-mmc
> + - const: allwinner,sun7i-a20-mmc
>
> reg:
> maxItems: 1
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 2/4] dt-bindings: mmc: sunxi: Add Allwinner F1c100s compatibles
2022-01-30 22:03 ` [PATCH v2 2/4] dt-bindings: mmc: sunxi: Add Allwinner F1c100s compatibles Jesse Taube
2022-01-31 9:45 ` Maxime Ripard
2022-01-31 10:19 ` Andre Przywara
@ 2022-02-09 21:15 ` Rob Herring
2 siblings, 0 replies; 12+ messages in thread
From: Rob Herring @ 2022-02-09 21:15 UTC (permalink / raw)
To: Jesse Taube
Cc: Mr.Bossman075, andre.przywara, linux-arm-kernel, devicetree,
robh+dt, mripard, linux-sunxi
On Sun, 30 Jan 2022 17:03:23 -0500, Jesse Taube wrote:
> Add binding for F1c100s's mmc controller.
>
> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
> ---
> V1 -> V2:
> * New commit
> ---
> .../devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml | 3 +++
> 1 file changed, 3 insertions(+)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 3/4] ARM: dtsi: suniv: Add mmc to f1c100s dtsi.
2022-01-30 22:03 [PATCH v2 1/4] ARM: dtsi: suniv: F1c100s add clock and reset macros Jesse Taube
2022-01-30 22:03 ` [PATCH v2 2/4] dt-bindings: mmc: sunxi: Add Allwinner F1c100s compatibles Jesse Taube
@ 2022-01-30 22:03 ` Jesse Taube
2022-01-31 9:46 ` Maxime Ripard
2022-01-31 10:14 ` Andre Przywara
2022-01-30 22:03 ` [PATCH v2 4/4] ARM: dts: suniv: Enable mmc for f1c100s Jesse Taube
2022-01-31 9:50 ` [PATCH v2 1/4] ARM: dtsi: suniv: F1c100s add clock and reset macros Andre Przywara
3 siblings, 2 replies; 12+ messages in thread
From: Jesse Taube @ 2022-01-30 22:03 UTC (permalink / raw)
To: devicetree
Cc: robh+dt, Mr.Bossman075, andre.przywara, linux-sunxi, mripard,
linux-arm-kernel
Add mmc0 and 1 for f1c100s dtsi.
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
---
V1 -> V2:
* Split patch
---
arch/arm/boot/dts/suniv-f1c100s.dtsi | 41 ++++++++++++++++++++++++++++
1 file changed, 41 insertions(+)
diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
index 953228cc8d52..60fa56c278a8 100644
--- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
@@ -96,6 +96,11 @@ uart0_pe_pins: uart0-pe-pins {
pins = "PE0", "PE1";
function = "uart0";
};
+
+ mmc0_pins: mmc0-pins {
+ pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
+ function = "mmc0";
+ };
};
timer@1c20c00 {
@@ -111,6 +116,42 @@ wdt: watchdog@1c20ca0 {
reg = <0x01c20ca0 0x20>;
};
+ mmc0: mmc@1c0f000 {
+ compatible = "allwinner,suniv-f1c100s-mmc",
+ "allwinner,sun7i-a20-mmc";
+ reg = <0x01c0f000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC0>,
+ <&ccu CLK_MMC0>,
+ <&ccu CLK_MMC0_OUTPUT>,
+ <&ccu CLK_MMC0_SAMPLE>;
+ clock-names = "ahb", "mmc", "output", "sample";
+ resets = <&ccu RST_BUS_MMC0>;
+ reset-names = "ahb";
+ interrupts = <23>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&mmc0_pins>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
+ mmc1: mmc@1c10000 {
+ compatible = "allwinner,suniv-f1c100s-mmc",
+ "allwinner,sun7i-a20-mmc";
+ reg = <0x01c10000 0x1000>;
+ clocks = <&ccu CLK_BUS_MMC1>,
+ <&ccu CLK_MMC1>,
+ <&ccu CLK_MMC1_OUTPUT>,
+ <&ccu CLK_MMC1_SAMPLE>;
+ clock-names = "ahb", "mmc", "output", "sample";
+ resets = <&ccu RST_BUS_MMC1>;
+ reset-names = "ahb";
+ interrupts = <24>;
+ status = "disabled";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+
uart0: serial@1c25000 {
compatible = "snps,dw-apb-uart";
reg = <0x01c25000 0x400>;
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v2 3/4] ARM: dtsi: suniv: Add mmc to f1c100s dtsi.
2022-01-30 22:03 ` [PATCH v2 3/4] ARM: dtsi: suniv: Add mmc to f1c100s dtsi Jesse Taube
@ 2022-01-31 9:46 ` Maxime Ripard
2022-01-31 10:14 ` Andre Przywara
1 sibling, 0 replies; 12+ messages in thread
From: Maxime Ripard @ 2022-01-31 9:46 UTC (permalink / raw)
To: Jesse Taube
Cc: devicetree, robh+dt, andre.przywara, linux-sunxi,
linux-arm-kernel
[-- Attachment #1: Type: text/plain, Size: 2206 bytes --]
Hi,
On Sun, Jan 30, 2022 at 05:03:24PM -0500, Jesse Taube wrote:
> Add mmc0 and 1 for f1c100s dtsi.
>
> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
> ---
> V1 -> V2:
> * Split patch
> ---
> arch/arm/boot/dts/suniv-f1c100s.dtsi | 41 ++++++++++++++++++++++++++++
> 1 file changed, 41 insertions(+)
>
> diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
> index 953228cc8d52..60fa56c278a8 100644
> --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
> +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
> @@ -96,6 +96,11 @@ uart0_pe_pins: uart0-pe-pins {
> pins = "PE0", "PE1";
> function = "uart0";
> };
> +
> + mmc0_pins: mmc0-pins {
> + pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
> + function = "mmc0";
> + };
Pinctrl nodes are ordered alphabetically
Also, you need to have a drive-strength of 30mA
> };
>
> timer@1c20c00 {
> @@ -111,6 +116,42 @@ wdt: watchdog@1c20ca0 {
> reg = <0x01c20ca0 0x20>;
> };
>
> + mmc0: mmc@1c0f000 {
> + compatible = "allwinner,suniv-f1c100s-mmc",
> + "allwinner,sun7i-a20-mmc";
> + reg = <0x01c0f000 0x1000>;
> + clocks = <&ccu CLK_BUS_MMC0>,
> + <&ccu CLK_MMC0>,
> + <&ccu CLK_MMC0_OUTPUT>,
> + <&ccu CLK_MMC0_SAMPLE>;
> + clock-names = "ahb", "mmc", "output", "sample";
> + resets = <&ccu RST_BUS_MMC0>;
> + reset-names = "ahb";
> + interrupts = <23>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc0_pins>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + mmc1: mmc@1c10000 {
> + compatible = "allwinner,suniv-f1c100s-mmc",
> + "allwinner,sun7i-a20-mmc";
> + reg = <0x01c10000 0x1000>;
> + clocks = <&ccu CLK_BUS_MMC1>,
> + <&ccu CLK_MMC1>,
> + <&ccu CLK_MMC1_OUTPUT>,
> + <&ccu CLK_MMC1_SAMPLE>;
> + clock-names = "ahb", "mmc", "output", "sample";
> + resets = <&ccu RST_BUS_MMC1>;
> + reset-names = "ahb";
> + interrupts = <24>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
And here, the nodes are ordered by register base address
Maxime
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^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v2 3/4] ARM: dtsi: suniv: Add mmc to f1c100s dtsi.
2022-01-30 22:03 ` [PATCH v2 3/4] ARM: dtsi: suniv: Add mmc to f1c100s dtsi Jesse Taube
2022-01-31 9:46 ` Maxime Ripard
@ 2022-01-31 10:14 ` Andre Przywara
1 sibling, 0 replies; 12+ messages in thread
From: Andre Przywara @ 2022-01-31 10:14 UTC (permalink / raw)
To: Jesse Taube; +Cc: devicetree, robh+dt, linux-sunxi, mripard, linux-arm-kernel
On Sun, 30 Jan 2022 17:03:24 -0500
Jesse Taube <mr.bossman075@gmail.com> wrote:
> Add mmc0 and 1 for f1c100s dtsi.
>
> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
The numbers looks alright, just one thing below:
> ---
> V1 -> V2:
> * Split patch
> ---
> arch/arm/boot/dts/suniv-f1c100s.dtsi | 41 ++++++++++++++++++++++++++++
> 1 file changed, 41 insertions(+)
>
> diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
> index 953228cc8d52..60fa56c278a8 100644
> --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
> +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
> @@ -96,6 +96,11 @@ uart0_pe_pins: uart0-pe-pins {
> pins = "PE0", "PE1";
> function = "uart0";
> };
> +
> + mmc0_pins: mmc0-pins {
> + pins = "PF0", "PF1", "PF2", "PF3", "PF4", "PF5";
> + function = "mmc0";
> + };
> };
>
> timer@1c20c00 {
> @@ -111,6 +116,42 @@ wdt: watchdog@1c20ca0 {
> reg = <0x01c20ca0 0x20>;
> };
>
> + mmc0: mmc@1c0f000 {
> + compatible = "allwinner,suniv-f1c100s-mmc",
> + "allwinner,sun7i-a20-mmc";
> + reg = <0x01c0f000 0x1000>;
> + clocks = <&ccu CLK_BUS_MMC0>,
> + <&ccu CLK_MMC0>,
> + <&ccu CLK_MMC0_OUTPUT>,
> + <&ccu CLK_MMC0_SAMPLE>;
> + clock-names = "ahb", "mmc", "output", "sample";
> + resets = <&ccu RST_BUS_MMC0>;
> + reset-names = "ahb";
The A20 does not have a reset control for the MMC controllers. It looks
like the Linux driver is fine with this (it always tries to get a reset
control, but treats it as optional), and the binding makes it optional for
all compatibles.
I just wonder if that would need to be strengthened in the binding? At the
cost of dropping the sun7i-a20-mmc fallback here? Or do we keep at least
the A20 supporting both, so that existing kernel can support this device?
Or do we not care and just keep the reset control deliberately optional
for all SoCs?
The other bits check out when compared to the manual, though the
full compatibility to the A20 is more a less an assumption at this point.
At least the clock story seems to match (non-calibrate, extra sample
clocks).
Cheers,
Andre
> + interrupts = <23>;
> + pinctrl-names = "default";
> + pinctrl-0 = <&mmc0_pins>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> + mmc1: mmc@1c10000 {
> + compatible = "allwinner,suniv-f1c100s-mmc",
> + "allwinner,sun7i-a20-mmc";
> + reg = <0x01c10000 0x1000>;
> + clocks = <&ccu CLK_BUS_MMC1>,
> + <&ccu CLK_MMC1>,
> + <&ccu CLK_MMC1_OUTPUT>,
> + <&ccu CLK_MMC1_SAMPLE>;
> + clock-names = "ahb", "mmc", "output", "sample";
> + resets = <&ccu RST_BUS_MMC1>;
> + reset-names = "ahb";
> + interrupts = <24>;
> + status = "disabled";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + };
> +
> uart0: serial@1c25000 {
> compatible = "snps,dw-apb-uart";
> reg = <0x01c25000 0x400>;
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH v2 4/4] ARM: dts: suniv: Enable mmc for f1c100s.
2022-01-30 22:03 [PATCH v2 1/4] ARM: dtsi: suniv: F1c100s add clock and reset macros Jesse Taube
2022-01-30 22:03 ` [PATCH v2 2/4] dt-bindings: mmc: sunxi: Add Allwinner F1c100s compatibles Jesse Taube
2022-01-30 22:03 ` [PATCH v2 3/4] ARM: dtsi: suniv: Add mmc to f1c100s dtsi Jesse Taube
@ 2022-01-30 22:03 ` Jesse Taube
2022-01-31 9:46 ` Maxime Ripard
2022-01-31 10:17 ` Andre Przywara
2022-01-31 9:50 ` [PATCH v2 1/4] ARM: dtsi: suniv: F1c100s add clock and reset macros Andre Przywara
3 siblings, 2 replies; 12+ messages in thread
From: Jesse Taube @ 2022-01-30 22:03 UTC (permalink / raw)
To: devicetree
Cc: robh+dt, Mr.Bossman075, andre.przywara, linux-sunxi, mripard,
linux-arm-kernel
Enable mmc0 in f1c100s-licheepi-nano device tree.
Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
---
V1 -> V2:
* New patch
---
arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
index a1154e6c7cb5..c856a6a20dc8 100644
--- a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
+++ b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
@@ -24,3 +24,9 @@ &uart0 {
pinctrl-0 = <&uart0_pe_pins>;
status = "okay";
};
+
+&mmc0 {
+ bus-width = <4>;
+ broken-cd;
+ status = "okay";
+};
--
2.34.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* Re: [PATCH v2 4/4] ARM: dts: suniv: Enable mmc for f1c100s.
2022-01-30 22:03 ` [PATCH v2 4/4] ARM: dts: suniv: Enable mmc for f1c100s Jesse Taube
@ 2022-01-31 9:46 ` Maxime Ripard
2022-01-31 10:17 ` Andre Przywara
1 sibling, 0 replies; 12+ messages in thread
From: Maxime Ripard @ 2022-01-31 9:46 UTC (permalink / raw)
To: Jesse Taube
Cc: devicetree, robh+dt, andre.przywara, linux-sunxi,
linux-arm-kernel
[-- Attachment #1: Type: text/plain, Size: 830 bytes --]
On Sun, Jan 30, 2022 at 05:03:25PM -0500, Jesse Taube wrote:
> Enable mmc0 in f1c100s-licheepi-nano device tree.
>
> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
> ---
> V1 -> V2:
> * New patch
> ---
> arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
> index a1154e6c7cb5..c856a6a20dc8 100644
> --- a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
> +++ b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
> @@ -24,3 +24,9 @@ &uart0 {
> pinctrl-0 = <&uart0_pe_pins>;
> status = "okay";
> };
> +
> +&mmc0 {
> + bus-width = <4>;
> + broken-cd;
> + status = "okay";
> +};
The labels are ordered alphabetically
Maxime
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^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH v2 4/4] ARM: dts: suniv: Enable mmc for f1c100s.
2022-01-30 22:03 ` [PATCH v2 4/4] ARM: dts: suniv: Enable mmc for f1c100s Jesse Taube
2022-01-31 9:46 ` Maxime Ripard
@ 2022-01-31 10:17 ` Andre Przywara
1 sibling, 0 replies; 12+ messages in thread
From: Andre Przywara @ 2022-01-31 10:17 UTC (permalink / raw)
To: Jesse Taube; +Cc: devicetree, robh+dt, linux-sunxi, mripard, linux-arm-kernel
On Sun, 30 Jan 2022 17:03:25 -0500
Jesse Taube <mr.bossman075@gmail.com> wrote:
> Enable mmc0 in f1c100s-licheepi-nano device tree.
>
> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
> ---
> V1 -> V2:
> * New patch
> ---
> arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
> index a1154e6c7cb5..c856a6a20dc8 100644
> --- a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
> +++ b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
> @@ -24,3 +24,9 @@ &uart0 {
> pinctrl-0 = <&uart0_pe_pins>;
> status = "okay";
> };
> +
> +&mmc0 {
> + bus-width = <4>;
> + broken-cd;
> + status = "okay";
Do we need a vmmc-supply?
Otherwise looks alright.
Cheers,
Andre
> +};
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [PATCH v2 1/4] ARM: dtsi: suniv: F1c100s add clock and reset macros
2022-01-30 22:03 [PATCH v2 1/4] ARM: dtsi: suniv: F1c100s add clock and reset macros Jesse Taube
` (2 preceding siblings ...)
2022-01-30 22:03 ` [PATCH v2 4/4] ARM: dts: suniv: Enable mmc for f1c100s Jesse Taube
@ 2022-01-31 9:50 ` Andre Przywara
3 siblings, 0 replies; 12+ messages in thread
From: Andre Przywara @ 2022-01-31 9:50 UTC (permalink / raw)
To: Jesse Taube; +Cc: devicetree, robh+dt, linux-sunxi, mripard, linux-arm-kernel
On Sun, 30 Jan 2022 17:03:22 -0500
Jesse Taube <mr.bossman075@gmail.com> wrote:
> Include clock and reset macros and replace magic numbers.
>
> Signed-off-by: Jesse Taube <Mr.Bossman075@gmail.com>
Checked that the numbers match the definitions in the header file, also
the generated .dtb files are identical.
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Cheers,
Andre
> ---
> arch/arm/boot/dts/suniv-f1c100s.dtsi | 17 ++++++++++-------
> 1 file changed, 10 insertions(+), 7 deletions(-)
>
> diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
> index 6100d3b75f61..953228cc8d52 100644
> --- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
> +++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
> @@ -4,6 +4,9 @@
> * Copyright 2018 Mesih Kilinc <mesihkilinc@gmail.com>
> */
>
> +#include <dt-bindings/clock/suniv-ccu-f1c100s.h>
> +#include <dt-bindings/reset/suniv-ccu-f1c100s.h>
> +
> / {
> #address-cells = <1>;
> #size-cells = <1>;
> @@ -82,7 +85,7 @@ pio: pinctrl@1c20800 {
> compatible = "allwinner,suniv-f1c100s-pinctrl";
> reg = <0x01c20800 0x400>;
> interrupts = <38>, <39>, <40>;
> - clocks = <&ccu 37>, <&osc24M>, <&osc32k>;
> + clocks = <&ccu CLK_BUS_PIO>, <&osc24M>, <&osc32k>;
> clock-names = "apb", "hosc", "losc";
> gpio-controller;
> interrupt-controller;
> @@ -114,8 +117,8 @@ uart0: serial@1c25000 {
> interrupts = <1>;
> reg-shift = <2>;
> reg-io-width = <4>;
> - clocks = <&ccu 38>;
> - resets = <&ccu 24>;
> + clocks = <&ccu CLK_BUS_UART0>;
> + resets = <&ccu RST_BUS_UART0>;
> status = "disabled";
> };
>
> @@ -125,8 +128,8 @@ uart1: serial@1c25400 {
> interrupts = <2>;
> reg-shift = <2>;
> reg-io-width = <4>;
> - clocks = <&ccu 39>;
> - resets = <&ccu 25>;
> + clocks = <&ccu CLK_BUS_UART1>;
> + resets = <&ccu RST_BUS_UART1>;
> status = "disabled";
> };
>
> @@ -136,8 +139,8 @@ uart2: serial@1c25800 {
> interrupts = <3>;
> reg-shift = <2>;
> reg-io-width = <4>;
> - clocks = <&ccu 40>;
> - resets = <&ccu 26>;
> + clocks = <&ccu CLK_BUS_UART2>;
> + resets = <&ccu RST_BUS_UART2>;
> status = "disabled";
> };
> };
^ permalink raw reply [flat|nested] 12+ messages in thread