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* [PATCH] ARM: dts: bcm2837: Add the missing L1/L2 cache information
@ 2021-12-18 20:00 Richard Schleich
  2021-12-28 17:52 ` Stefan Wahren
  2022-02-01  0:24 ` Florian Fainelli
  0 siblings, 2 replies; 4+ messages in thread
From: Richard Schleich @ 2021-12-18 20:00 UTC (permalink / raw)
  To: robh+dt, nsaenz, f.fainelli, bcm-kernel-feedback-list, devicetree,
	linux-rpi-kernel, linux-arm-kernel
  Cc: Richard Schleich

This patch fixes the kernel warning
"cacheinfo: Unable to detect cache hierarchy for CPU 0"
for the bcm2837 on newer kernel versions.

Signed-off-by: Richard Schleich <rs@noreya.tech>
---
 arch/arm/boot/dts/bcm2837.dtsi | 49 ++++++++++++++++++++++++++++++++++
 1 file changed, 49 insertions(+)

diff --git a/arch/arm/boot/dts/bcm2837.dtsi b/arch/arm/boot/dts/bcm2837.dtsi
index 0199ec98cd61..1af1616982bb 100644
--- a/arch/arm/boot/dts/bcm2837.dtsi
+++ b/arch/arm/boot/dts/bcm2837.dtsi
@@ -40,12 +40,26 @@
 		#size-cells = <0>;
 		enable-method = "brcm,bcm2836-smp"; // for ARM 32-bit
 
+		/* Source for d/i-cache-line-size and d/i-cache-sets
+		 *  https://developer.arm.com/documentation/ddi0500/e/level-1-memory-system
+		 *  /about-the-l1-memory-system?lang=en
+		 *
+		 *  Source for d/i-cache-size
+		 *  https://magpi.raspberrypi.com/articles/raspberry-pi-3-specs-benchmarks
+		 */
 		cpu0: cpu@0 {
 			device_type = "cpu";
 			compatible = "arm,cortex-a53";
 			reg = <0>;
 			enable-method = "spin-table";
 			cpu-release-addr = <0x0 0x000000d8>;
+			d-cache-size = <0x8000>; // 32KiB
+			d-cache-line-size = <64>;// Data side cache line length of 64 bytes
+			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
+			i-cache-size = <0x8000>; // 32KiB
+			i-cache-line-size = <64>;// Instruction side cache line length of 64 bytes
+			i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
+			next-level-cache = <&l2>;
 		};
 
 		cpu1: cpu@1 {
@@ -54,6 +68,13 @@
 			reg = <1>;
 			enable-method = "spin-table";
 			cpu-release-addr = <0x0 0x000000e0>;
+			d-cache-size = <0x8000>; // 32KiB
+			d-cache-line-size = <64>;// Data side cache line length of 64 bytes
+			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
+			i-cache-size = <0x8000>; // 32KiB
+			i-cache-line-size = <64>;// Instruction side cache line length of 64 bytes
+			i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
+			next-level-cache = <&l2>;
 		};
 
 		cpu2: cpu@2 {
@@ -62,6 +83,13 @@
 			reg = <2>;
 			enable-method = "spin-table";
 			cpu-release-addr = <0x0 0x000000e8>;
+			d-cache-size = <0x8000>; // 32KiB
+			d-cache-line-size = <64>;// Data side cache line length of 64 bytes
+			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
+			i-cache-size = <0x8000>; // 32KiB
+			i-cache-line-size = <64>;// Instruction side cache line length of 64 bytes
+			i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
+			next-level-cache = <&l2>;
 		};
 
 		cpu3: cpu@3 {
@@ -70,6 +98,27 @@
 			reg = <3>;
 			enable-method = "spin-table";
 			cpu-release-addr = <0x0 0x000000f0>;
+			d-cache-size = <0x8000>; // 32KiB
+			d-cache-line-size = <64>;// Data side cache line length of 64 bytes
+			d-cache-sets = <128>; // 32KiB(size)/64(line-size)=512ways/4-way set
+			i-cache-size = <0x8000>; // 32KiB
+			i-cache-line-size = <64>;// Instruction side cache line length of 64 bytes
+			i-cache-sets = <256>; // 32KiB(size)/64(line-size)=512ways/2-way set
+			next-level-cache = <&l2>;
+		};
+
+		l2: l2-cache0 {
+		 /*  Source for cache-line-size + cache-sets
+		  *  https://developer.arm.com/documentation/ddi0500
+		  *  /e/level-2-memory-system/about-the-l2-memory-system?lang=en
+		  *  Source for cache-size
+		  *  https://datasheets.raspberrypi.com/cm/cm1-and-cm3-datasheet.pdf
+		  */
+			compatible = "cache";
+			cache-size = <0x80000>; // 512KiB
+			cache-line-size = <64>; // Fixed line length of 64 bytes
+			cache-sets = <512>; // 512KiB(size)/64(line-size)=8192ways/16-way set
+			cache-level = <2>;
 		};
 	};
 };
-- 
2.17.1


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2021-12-18 20:00 [PATCH] ARM: dts: bcm2837: Add the missing L1/L2 cache information Richard Schleich
2021-12-28 17:52 ` Stefan Wahren
2022-02-01  0:24 ` Florian Fainelli
2022-02-01  0:29   ` Florian Fainelli

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