[PATCH v2 1/2] clk: qcom: clk-rcg2: Update the calc_rate logic to handle determine rate

[PATCH v2 1/2] clk: qcom: clk-rcg2: Update the calc_rate logic to handle determine rate

[Taniya Das]

In the cases where the RCG parent implements the determine rate ops, the
calc_rate needs to be updated the calculate the rate.

Fixes: bcd61c0f535a0 ("clk: qcom: Add support for root clock generators (RCGs)")
Signed-off-by: Taniya Das <tdas@codeaurora.org>
---
 * Split the patch for PLL and RCG.
 * Update the Fixes tag.

 drivers/clk/qcom/clk-rcg2.c | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index e1b1b426fae4..2e120a6dd19a 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -147,19 +147,19 @@ static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index)
 static unsigned long
 calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div)
 {
+	u64 tmp = rate;
+
 	if (hid_div) {
-		rate *= 2;
-		rate /= hid_div + 1;
+		tmp *= 2;
+		do_div(tmp, hid_div + 1);
 	}

 	if (mode) {
-		u64 tmp = rate;
 		tmp *= m;
 		do_div(tmp, n);
-		rate = tmp;
 	}

-	return rate;
+	return tmp;
 }

 static unsigned long
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the  Linux Foundation.

[PATCH v2 2/2] clk: qcom: clk-alpha-pll: Update to use determine rate ops for PLL

[Taniya Das]

On 32 bit devices, where the PLL requires to support the frequency
beyond the range of the `long int` the round rate ops cannot support.
Thus update the clk_ops to use determine rate instead.

Fixes: 134b55b7e19f8 ("clk: qcom: support Huayra type Alpha PLL")
Signed-off-by: Taniya Das <tdas@codeaurora.org>
---
 drivers/clk/qcom/clk-alpha-pll.c | 21 +++++++++++++++++----
 1 file changed, 17 insertions(+), 4 deletions(-)

diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
index 4406cf609aae..4e2e93cd8c8b 100644
--- a/drivers/clk/qcom/clk-alpha-pll.c
+++ b/drivers/clk/qcom/clk-alpha-pll.c
@@ -812,12 +812,25 @@ static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate,
 	return 0;
 }

-static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate,
-					unsigned long *prate)
+static int alpha_pll_huayra_determine_rate(struct clk_hw *hw,
+					struct clk_rate_request *req)
 {
+	struct clk_hw *parent_hw;
+	unsigned long rrate, prate;
 	u32 l, a;

-	return alpha_huayra_pll_round_rate(rate, *prate, &l, &a);
+	parent_hw = clk_hw_get_parent(hw);
+	if (!parent_hw)
+		return -EINVAL;
+
+	prate = clk_hw_get_rate(parent_hw);
+	rrate = alpha_huayra_pll_round_rate(req->rate, prate, &l, &a);
+
+	req->best_parent_hw = parent_hw;
+	req->best_parent_rate = prate;
+	req->rate = rrate;
+
+	return 0;
 }

 static int trion_pll_is_enabled(struct clk_alpha_pll *pll,
@@ -946,7 +959,7 @@ const struct clk_ops clk_alpha_pll_huayra_ops = {
 	.disable = clk_alpha_pll_disable,
 	.is_enabled = clk_alpha_pll_is_enabled,
 	.recalc_rate = alpha_pll_huayra_recalc_rate,
-	.round_rate = alpha_pll_huayra_round_rate,
+	.determine_rate = alpha_pll_huayra_determine_rate,
 	.set_rate = alpha_pll_huayra_set_rate,
 };
 EXPORT_SYMBOL_GPL(clk_alpha_pll_huayra_ops);
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member
of the Code Aurora Forum, hosted by the  Linux Foundation.

Re: [PATCH v2 1/2] clk: qcom: clk-rcg2: Update the calc_rate logic to handle determine rate

[Stephen Boyd]

Quoting Taniya Das (2022-02-02 09:42:12)
> In the cases where the RCG parent implements the determine rate ops, the
> calc_rate needs to be updated the calculate the rate.

I don't follow. Do you mean in cases where 'rate' is close to 32-bits
and we're running on a CPU with sizeof(long) == u32?

> 
> Fixes: bcd61c0f535a0 ("clk: qcom: Add support for root clock generators (RCGs)")
> Signed-off-by: Taniya Das <tdas@codeaurora.org>
> ---
>  * Split the patch for PLL and RCG.
>  * Update the Fixes tag.
> 
>  drivers/clk/qcom/clk-rcg2.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
> index e1b1b426fae4..2e120a6dd19a 100644
> --- a/drivers/clk/qcom/clk-rcg2.c
> +++ b/drivers/clk/qcom/clk-rcg2.c
> @@ -147,19 +147,19 @@ static int clk_rcg2_set_parent(struct clk_hw *hw, u8 index)
>  static unsigned long
>  calc_rate(unsigned long rate, u32 m, u32 n, u32 mode, u32 hid_div)
>  {
> +       u64 tmp = rate;

Call it u64 calced_rate or u64 calculated?

> +
>         if (hid_div) {
> -               rate *= 2;
> -               rate /= hid_div + 1;
> +               tmp *= 2;
> +               do_div(tmp, hid_div + 1);

Can this use div_u64()?

>         }
> 
>         if (mode) {
> -               u64 tmp = rate;
>                 tmp *= m;
>                 do_div(tmp, n);

This can probably use div_u64() as well. Do that first in a different
patch and then put this patch on top please.

> -               rate = tmp;
>         }
> 
> -       return rate;
> +       return tmp;
>  }

Re: [PATCH v2 2/2] clk: qcom: clk-alpha-pll: Update to use determine rate ops for PLL

[Stephen Boyd]

Quoting Taniya Das (2022-02-02 09:42:13)
> diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c
> index 4406cf609aae..4e2e93cd8c8b 100644
> --- a/drivers/clk/qcom/clk-alpha-pll.c
> +++ b/drivers/clk/qcom/clk-alpha-pll.c
> @@ -812,12 +812,25 @@ static int alpha_pll_huayra_set_rate(struct clk_hw *hw, unsigned long rate,
>         return 0;
>  }
> 
> -static long alpha_pll_huayra_round_rate(struct clk_hw *hw, unsigned long rate,
> -                                       unsigned long *prate)
> +static int alpha_pll_huayra_determine_rate(struct clk_hw *hw,
> +                                       struct clk_rate_request *req)
>  {
> +       struct clk_hw *parent_hw;
> +       unsigned long rrate, prate;
>         u32 l, a;
> 
> -       return alpha_huayra_pll_round_rate(rate, *prate, &l, &a);
> +       parent_hw = clk_hw_get_parent(hw);

The clk_rate_request should already have the parent_hw pointer set in
it. See clk_core_init_rate_req(). So there's no need to
clk_hw_get_parent() again here.

> +       if (!parent_hw)
> +               return -EINVAL;
> +
> +       prate = clk_hw_get_rate(parent_hw);

And low and behold the parent rate is also prepopulated in 'req'. Just
use that.

> +       rrate = alpha_huayra_pll_round_rate(req->rate, prate, &l, &a);
> +
> +       req->best_parent_hw = parent_hw;

Remove.

> +       req->best_parent_rate = prate;

Remove.

> +       req->rate = rrate;

Keep.

	req->rate = alpha_pll_huayra_round_rate(req->rate, prate, &l, &a);

> +
> +       return 0;
>  }
> 
>  static int trion_pll_is_enabled(struct clk_alpha_pll *pll,