From: Michael Walle <michael@walle.cc>
To: kavyasree.kotagiri@microchip.com
Cc: Manohar.Puri@microchip.com, UNGLinuxDriver@microchip.com,
alexandre.belloni@bootlin.com, arnd@arndb.de,
devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, nicolas.ferre@microchip.com,
olof@lixom.net, robh+dt@kernel.org, soc@kernel.org,
Michael Walle <michael@walle.cc>
Subject: Re: [PATCH v4] ARM: dts: add DT for lan966 SoC and 2-port board pcb8291
Date: Wed, 9 Feb 2022 19:46:00 +0100 [thread overview]
Message-ID: <20220209184600.1230365-1-michael@walle.cc> (raw)
In-Reply-To: <20220209111318.21112-1-kavyasree.kotagiri@microchip.com>
Hi,
> + clocks {
[..]
> +
> + nic_clk: nic_clk {
What does nic_clk stand for? If I had to guess, it
has something to do with network. But..
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + clock-frequency = <200000000>;
> + };
> + };
> +
> + clks: clock-controller@e00c00a8 {
> + compatible = "microchip,lan966x-gck";
> + #clock-cells = <1>;
> + clocks = <&cpu_clk>, <&ddr_clk>, <&sys_clk>;
> + clock-names = "cpu", "ddr", "sys";
> + reg = <0xe00c00a8 0x38>;
> + };
> +
> + timer {
> + compatible = "arm,armv7-timer";
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
> + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
> + clock-frequency = <37500000>;
> + arm,cpu-registers-not-fw-configured;
> + };
> +
> + soc {
> + compatible = "simple-bus";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges;
> +
> + flx0: flexcom@e0040000 {
> + compatible = "atmel,sama5d2-flexcom";
> + reg = <0xe0040000 0x100>;
> + clocks = <&clks GCK_ID_FLEXCOM0>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0xe0040000 0x800>;
> + status = "disabled";
> + };
> +
> + flx1: flexcom@e0044000 {
> + compatible = "atmel,sama5d2-flexcom";
> + reg = <0xe0044000 0x100>;
> + clocks = <&clks GCK_ID_FLEXCOM1>;
> + #address-cells = <1>;
> + #size-cells = <1>;
> + ranges = <0x0 0xe0044000 0x800>;
> + status = "disabled";
> + };
> +
> + trng: trng@e0048000 {
> + compatible = "atmel,at91sam9g45-trng";
> + reg = <0xe0048000 0x100>;
> + clocks = <&nic_clk>;
.. it is used here..
> + };
> +
> + aes: aes@e004c000 {
> + compatible = "atmel,at91sam9g46-aes";
> + reg = <0xe004c000 0x100>;
> + interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
> + dmas = <&dma0 AT91_XDMAC_DT_PERID(13)>,
> + <&dma0 AT91_XDMAC_DT_PERID(12)>;
> + dma-names = "rx", "tx";
> + clocks = <&nic_clk>;
.. and here. and so on.
So, is it some kind of internal clock?
> + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
> + };
> +
> + watchdog: watchdog@e0090000 {
> + compatible = "snps,dw-wdt";
> + reg = <0xe0090000 0x1000>;
> + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&nic_clk>;
Btw. can we disable all nodes by default and enable them
in the board dts files?
next prev parent reply other threads:[~2022-02-09 18:52 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-09 11:13 [PATCH v4] ARM: dts: add DT for lan966 SoC and 2-port board pcb8291 Kavyasree Kotagiri
2022-02-09 12:32 ` Tudor.Ambarus
2022-02-10 12:37 ` Michael Walle
2022-02-10 13:02 ` Kavyasree.Kotagiri
2022-02-10 13:33 ` Michael Walle
2022-02-18 10:55 ` Kavyasree.Kotagiri
2022-02-09 18:46 ` Michael Walle [this message]
2022-02-10 9:40 ` Kavyasree.Kotagiri
2022-02-10 9:50 ` Michael Walle
2022-02-10 11:52 ` Kavyasree.Kotagiri
2022-02-10 12:05 ` Michael Walle
2022-02-18 12:28 ` Kavyasree.Kotagiri
2022-02-18 12:32 ` Michael Walle
2022-02-21 5:44 ` Kavyasree.Kotagiri
2022-02-21 7:28 ` Michael Walle
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