* [PATCH 3/8] dt-bindings: clock: Add A7 PLL binding for SDX65
@ 2022-02-14 6:57 Rohit Agarwal
2022-02-14 8:35 ` Manivannan Sadhasivam
0 siblings, 1 reply; 2+ messages in thread
From: Rohit Agarwal @ 2022-02-14 6:57 UTC (permalink / raw)
To: agross, bjorn.andersson, mturquette, sboyd, robh+dt,
manivannan.sadhasivam
Cc: linux-arm-msm, linux-clk, devicetree, linux-kernel, Rohit Agarwal
Add YAML binding for Cortex A7 PLL clock in Qualcomm
platforms like SDX65.
Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
---
Documentation/devicetree/bindings/clock/qcom,a7pll.yaml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml b/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml
index 8666e99..b8889dc 100644
--- a/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml
@@ -10,13 +10,14 @@ maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
description:
- The A7 PLL on the Qualcomm platforms like SDX55 is used to provide high
+ The A7 PLL on the Qualcomm platforms like SDX55, SDX65 is used to provide high
frequency clock to the CPU.
properties:
compatible:
enum:
- qcom,sdx55-a7pll
+ - qcom,sdx65-a7pll
reg:
maxItems: 1
--
2.7.4
^ permalink raw reply related [flat|nested] 2+ messages in thread* Re: [PATCH 3/8] dt-bindings: clock: Add A7 PLL binding for SDX65
2022-02-14 6:57 [PATCH 3/8] dt-bindings: clock: Add A7 PLL binding for SDX65 Rohit Agarwal
@ 2022-02-14 8:35 ` Manivannan Sadhasivam
0 siblings, 0 replies; 2+ messages in thread
From: Manivannan Sadhasivam @ 2022-02-14 8:35 UTC (permalink / raw)
To: Rohit Agarwal
Cc: agross, bjorn.andersson, mturquette, sboyd, robh+dt,
linux-arm-msm, linux-clk, devicetree, linux-kernel
On Mon, Feb 14, 2022 at 12:27:49PM +0530, Rohit Agarwal wrote:
> Add YAML binding for Cortex A7 PLL clock in Qualcomm
> platforms like SDX65.
>
> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Thanks,
Mani
> ---
> Documentation/devicetree/bindings/clock/qcom,a7pll.yaml | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml b/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml
> index 8666e99..b8889dc 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,a7pll.yaml
> @@ -10,13 +10,14 @@ maintainers:
> - Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
>
> description:
> - The A7 PLL on the Qualcomm platforms like SDX55 is used to provide high
> + The A7 PLL on the Qualcomm platforms like SDX55, SDX65 is used to provide high
> frequency clock to the CPU.
>
> properties:
> compatible:
> enum:
> - qcom,sdx55-a7pll
> + - qcom,sdx65-a7pll
>
> reg:
> maxItems: 1
> --
> 2.7.4
>
^ permalink raw reply [flat|nested] 2+ messages in thread
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