From: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
To: Rohit Agarwal <quic_rohiagar@quicinc.com>
Cc: agross@kernel.org, bjorn.andersson@linaro.org,
robh+dt@kernel.org, linux-arm-msm@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH 5/8] ARM: dts: qcom: sdx65: Add support for A7 PLL clock
Date: Mon, 14 Feb 2022 14:13:34 +0530 [thread overview]
Message-ID: <20220214084334.GE3494@thinkpad> (raw)
In-Reply-To: <1644822069-27513-1-git-send-email-quic_rohiagar@quicinc.com>
On Mon, Feb 14, 2022 at 12:31:09PM +0530, Rohit Agarwal wrote:
> On SDX65 there is a separate A7 PLL which is used to provide high
> frequency clock to the Cortex A7 CPU via a MUX.
>
> Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Thanks,
Mani
> ---
> arch/arm/boot/dts/qcom-sdx65.dtsi | 8 ++++++++
> 1 file changed, 8 insertions(+)
>
> diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi
> index 556a2e3..2900ffe 100644
> --- a/arch/arm/boot/dts/qcom-sdx65.dtsi
> +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi
> @@ -125,6 +125,14 @@
> <0x17802000 0x1000>;
> };
>
> + a7pll: clock@17808000 {
> + compatible = "qcom,sdx65-a7pll";
> + reg = <0x17808000 0x1000>;
> + clocks = <&rpmhcc RPMH_CXO_CLK>;
> + clock-names = "bi_tcxo";
> + #clock-cells = <0>;
> + };
> +
> timer@17820000 {
> #address-cells = <1>;
> #size-cells = <1>;
> --
> 2.7.4
>
prev parent reply other threads:[~2022-02-14 8:43 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-14 7:01 [PATCH 5/8] ARM: dts: qcom: sdx65: Add support for A7 PLL clock Rohit Agarwal
2022-02-14 8:43 ` Manivannan Sadhasivam [this message]
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