From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 60953C43219 for ; Mon, 14 Feb 2022 13:56:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1353190AbiBNN4i (ORCPT ); Mon, 14 Feb 2022 08:56:38 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:36058 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1354661AbiBNN4g (ORCPT ); Mon, 14 Feb 2022 08:56:36 -0500 Received: from esa.microchip.iphmx.com (esa.microchip.iphmx.com [68.232.154.123]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 445A6CFD; Mon, 14 Feb 2022 05:56:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=microchip.com; i=@microchip.com; q=dns/txt; s=mchp; t=1644846988; x=1676382988; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=RaK9SgN0U8rRaE6oOJFFvGb1cgu8ENs7J984QpIB3As=; b=EnYj5pzAYpyh3fAYnj3eVJkW5P/3bAkcwN8NKiIG1CJI0zTmJ4lB5ecr eRQ/qPHdepb6kiFBjigpvnKkjXuF1WFJABC9YzJlVeOzJCkBWrW6e/2sZ RXQD7tK2gbi1d2NrCYUpQXs2KvnZy5hYg6QefpqQkF1dCBGUVhyG3tMZb cupuIw45DlWr+HszxH0upb3yubu6nD1Aox9BWJQsQ871ClutIOchTup8R Q/NKsuIgZHZ2XrIIbrmi5mdUZEw3mnKAqe1JWdSw2amOcI8JQsdOo4KWt vKBp9z5U4dh+QlOHLfGzxkEDComHT+RiTgs0Fu3q9Hb6xTNXLyDyOySf6 g==; IronPort-SDR: UP5KAEpJ3QOcSjMg3QuPd61GIGkyeewE8UHSU9XeSWWk50jsqpHf/7+D7ASRM3R73rdp42cLOW cSAgOuyKQv7pL1h/kgLL6tI4yTWovmE1zetPbdlJ/KlF2IoNhvCqnpyZdOGW9e4thGsOXELtdm NDiyFsGmZ9MpE00JliaQ+y3eCP05giZNtvSG64CrtqxeOswMT6Nzr7zIED+zakBcfkWKCbhicP WLnzqqN6YeAMJZbMUnbQ53gzruvj1boWeyZDU1NNVYBqC2Jm6KK2uZKBTC2V/F9tiYLY+FgiyJ EUzkkukbWLETXAHDIHr08rSC X-IronPort-AV: E=Sophos;i="5.88,368,1635231600"; d="scan'208";a="148618016" Received: from smtpout.microchip.com (HELO email.microchip.com) ([198.175.253.82]) by esa2.microchip.iphmx.com with ESMTP/TLS/AES256-SHA256; 14 Feb 2022 06:56:22 -0700 Received: from chn-vm-ex04.mchp-main.com (10.10.85.152) by chn-vm-ex03.mchp-main.com (10.10.85.151) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.17; Mon, 14 Feb 2022 06:56:21 -0700 Received: from wendy.microchip.com (10.10.115.15) by chn-vm-ex04.mchp-main.com (10.10.85.152) with Microsoft SMTP Server id 15.1.2375.17 via Frontend Transport; Mon, 14 Feb 2022 06:56:16 -0700 From: To: , , , , , , , , , , , , , , , , , , , CC: , , , , , Palmer Dabbelt , Rob Herring Subject: [PATCH v7 03/11] dt-bindings: rtc: add bindings for microchip mpfs rtc Date: Mon, 14 Feb 2022 13:58:33 +0000 Message-ID: <20220214135840.168236-4-conor.dooley@microchip.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220214135840.168236-1-conor.dooley@microchip.com> References: <20220214135840.168236-1-conor.dooley@microchip.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Conor Dooley Add device tree bindings for the real time clock on the Microchip PolarFire SoC. Signed-off-by: Daire McNamara Signed-off-by: Conor Dooley Acked-by: Palmer Dabbelt Reviewed-by: Rob Herring --- .../bindings/rtc/microchip,mfps-rtc.yaml | 58 +++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml diff --git a/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml new file mode 100644 index 000000000000..a2e984ea3553 --- /dev/null +++ b/Documentation/devicetree/bindings/rtc/microchip,mfps-rtc.yaml @@ -0,0 +1,58 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rtc/microchip,mfps-rtc.yaml# + +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Microchip PolarFire Soc (MPFS) RTC Device Tree Bindings + +allOf: + - $ref: rtc.yaml# + +maintainers: + - Daire McNamara + - Lewis Hanly + +properties: + compatible: + enum: + - microchip,mpfs-rtc + + reg: + maxItems: 1 + + interrupts: + items: + - description: | + RTC_WAKEUP interrupt + - description: | + RTC_MATCH, asserted when the content of the Alarm register is equal + to that of the RTC's count register. + + clocks: + maxItems: 1 + + clock-names: + items: + - const: rtc + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + rtc@20124000 { + compatible = "microchip,mpfs-rtc"; + reg = <0x20124000 0x1000>; + clocks = <&clkcfg 21>; + clock-names = "rtc"; + interrupts = <80>, <81>; + }; +... -- 2.35.1