From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id E25CDC433EF for ; Tue, 15 Feb 2022 09:02:36 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232875AbiBOJCo (ORCPT ); Tue, 15 Feb 2022 04:02:44 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:41450 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S235526AbiBOJCm (ORCPT ); Tue, 15 Feb 2022 04:02:42 -0500 Received: from mail-qt1-x829.google.com (mail-qt1-x829.google.com [IPv6:2607:f8b0:4864:20::829]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id F2D24115948 for ; Tue, 15 Feb 2022 01:02:32 -0800 (PST) Received: by mail-qt1-x829.google.com with SMTP id s1so17905598qtw.9 for ; Tue, 15 Feb 2022 01:02:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6U4rijSjm5U8GLHq/t1MdTXdgQmgucjQmV8Ymo3NwgE=; b=d6AqXpyQAUkwb7NXhHhPGHpTrpz3kInmKc5l+9JKzydHa1Yjbsy2BRjVcrrntoh+uV YSQEMzX9r2CZNmJmFCHPm+X5kRBzgTrZM02dq9yoSvrYlt7uRDIMi7wlJLYJE7nizXzu aYhyLgumMIBE/xOUIwG9y/Z4cXW7mmh0UdF/CzdS7XB+Ck7zFP01JNJ19/P1gKt7YD3D 7hyGx4x7oSLcY1P5xdXeceqdoBd7KXOMfRoYuKL1/FOYYXCS14RqfWH01+GK6FFBzypt 8KllIXTC2VopZSJX1gQ/d3NwidFhmksqid4R56q62/Y6aJliP/uD5fXLPByPaBNiDRGF +DyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6U4rijSjm5U8GLHq/t1MdTXdgQmgucjQmV8Ymo3NwgE=; b=O9zfl9QHq8RbsXlLcY1ZzxuHNWLr9in126PKE3abEOiRDVCafFFQ5UUMYBLUQnjmqR jIF3vExlbBrouTE6Gr/q4o0k/XiKqbx2FDz5bVhW4gafJptL756Um3C4qc4Uvmn8O0mL 6VQS8uj71pH6d4ccONVLBwpwf7Gws6EZQwgM5Jj5SpqYZRyiRNM+xtjTeg5kTitlTUlF Lx3Ubud98WmMyEZBnlLYFHsr3QAA8o3pi/Ns6Rncest+XuvMp6mfio5fY+zKg3o1mtIx 47XPYLIDRepOexrtHSMe5eZ3aYW3KM0cZ4lshPe/hwzWjarkNzvNd9uB5ooevh0xli8/ epbQ== X-Gm-Message-State: AOAM531dtp+mCpO0V2LOLa2NkC1vwc9mOspGga5oAXLW8G+MXLtTZXdx sQAALixcGnK8c46UgwN7La9E8g== X-Google-Smtp-Source: ABdhPJx4/yvXhJ/ovAf24/YgwDAEuc6OS7o3jsbBhcLP6CiFPWkQQ7xGpHWTW3PyyVI01ETcK1YUEw== X-Received: by 2002:a05:622a:1350:: with SMTP id w16mr1988487qtk.320.1644915752185; Tue, 15 Feb 2022 01:02:32 -0800 (PST) Received: from rivos-atish.. (adsl-70-228-75-190.dsl.akrnoh.ameritech.net. [70.228.75.190]) by smtp.gmail.com with ESMTPSA id w4sm17711158qko.123.2022.02.15.01.02.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Feb 2022 01:02:31 -0800 (PST) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Tsukasa OI , Atish Patra , Heiko Stuebner , Albert Ou , Atish Patra , Anup Patel , Damien Le Moal , devicetree@vger.kernel.org, Jisheng Zhang , Krzysztof Kozlowski , linux-riscv@lists.infradead.org, Palmer Dabbelt , Paul Walmsley , Rob Herring Subject: [PATCH v3 1/6] RISC-V: Correctly print supported extensions Date: Tue, 15 Feb 2022 01:02:06 -0800 Message-Id: <20220215090211.911366-2-atishp@rivosinc.com> X-Mailer: git-send-email 2.30.2 In-Reply-To: <20220215090211.911366-1-atishp@rivosinc.com> References: <20220215090211.911366-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org From: Tsukasa OI This commit replaces BITS_PER_LONG with number of alphabet letters. Current ISA pretty-printing code expects extension 'a' (bit 0) through 'z' (bit 25). Although bit 26 and higher is not currently used (thus never cause an issue in practice), it will be an annoying problem if we start to use those in the future. This commit disables printing high bits for now. Signed-off-by: Tsukasa OI Signed-off-by: Atish Patra Tested-by: Heiko Stuebner --- arch/riscv/kernel/cpufeature.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c index d959d207a40d..dd3d57eb4eea 100644 --- a/arch/riscv/kernel/cpufeature.c +++ b/arch/riscv/kernel/cpufeature.c @@ -13,6 +13,8 @@ #include #include +#define NUM_ALPHA_EXTS ('z' - 'a' + 1) + unsigned long elf_hwcap __read_mostly; /* Host ISA bitmap */ @@ -63,7 +65,7 @@ void __init riscv_fill_hwcap(void) { struct device_node *node; const char *isa; - char print_str[BITS_PER_LONG + 1]; + char print_str[NUM_ALPHA_EXTS + 1]; size_t i, j, isa_len; static unsigned long isa2hwcap[256] = {0}; @@ -133,13 +135,13 @@ void __init riscv_fill_hwcap(void) } memset(print_str, 0, sizeof(print_str)); - for (i = 0, j = 0; i < BITS_PER_LONG; i++) + for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++) if (riscv_isa[0] & BIT_MASK(i)) print_str[j++] = (char)('a' + i); pr_info("riscv: ISA extensions %s\n", print_str); memset(print_str, 0, sizeof(print_str)); - for (i = 0, j = 0; i < BITS_PER_LONG; i++) + for (i = 0, j = 0; i < NUM_ALPHA_EXTS; i++) if (elf_hwcap & BIT_MASK(i)) print_str[j++] = (char)('a' + i); pr_info("riscv: ELF capabilities %s\n", print_str); -- 2.30.2