From: Atish Patra <atishp@rivosinc.com>
To: linux-kernel@vger.kernel.org
Cc: Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@rivosinc.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Atish Patra <atishp@atishpatra.org>,
Damien Le Moal <damien.lemoal@wdc.com>,
devicetree@vger.kernel.org, Jisheng Zhang <jszhang@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>,
linux-riscv@lists.infradead.org,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Rob Herring <robh+dt@kernel.org>
Subject: [v6 2/9] RISC-V: Add CSR encodings for all HPMCOUNTERS
Date: Fri, 18 Feb 2022 16:46:53 -0800 [thread overview]
Message-ID: <20220219004700.1973682-3-atishp@rivosinc.com> (raw)
In-Reply-To: <20220219004700.1973682-1-atishp@rivosinc.com>
From: Atish Patra <atish.patra@wdc.com>
Linux kernel can directly read these counters as the HPMCOUNTERS CSRs are
accessible in S-mode.
Reviewed-by: Anup Patel <anup@brainfault.org>
Signed-off-by: Atish Patra <atish.patra@wdc.com>
Signed-off-by: Atish Patra <atishp@rivosinc.com>
---
arch/riscv/include/asm/csr.h | 58 ++++++++++++++++++++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h
index ae711692eec9..ce493df11177 100644
--- a/arch/riscv/include/asm/csr.h
+++ b/arch/riscv/include/asm/csr.h
@@ -150,9 +150,67 @@
#define CSR_CYCLE 0xc00
#define CSR_TIME 0xc01
#define CSR_INSTRET 0xc02
+#define CSR_HPMCOUNTER3 0xc03
+#define CSR_HPMCOUNTER4 0xc04
+#define CSR_HPMCOUNTER5 0xc05
+#define CSR_HPMCOUNTER6 0xc06
+#define CSR_HPMCOUNTER7 0xc07
+#define CSR_HPMCOUNTER8 0xc08
+#define CSR_HPMCOUNTER9 0xc09
+#define CSR_HPMCOUNTER10 0xc0a
+#define CSR_HPMCOUNTER11 0xc0b
+#define CSR_HPMCOUNTER12 0xc0c
+#define CSR_HPMCOUNTER13 0xc0d
+#define CSR_HPMCOUNTER14 0xc0e
+#define CSR_HPMCOUNTER15 0xc0f
+#define CSR_HPMCOUNTER16 0xc10
+#define CSR_HPMCOUNTER17 0xc11
+#define CSR_HPMCOUNTER18 0xc12
+#define CSR_HPMCOUNTER19 0xc13
+#define CSR_HPMCOUNTER20 0xc14
+#define CSR_HPMCOUNTER21 0xc15
+#define CSR_HPMCOUNTER22 0xc16
+#define CSR_HPMCOUNTER23 0xc17
+#define CSR_HPMCOUNTER24 0xc18
+#define CSR_HPMCOUNTER25 0xc19
+#define CSR_HPMCOUNTER26 0xc1a
+#define CSR_HPMCOUNTER27 0xc1b
+#define CSR_HPMCOUNTER28 0xc1c
+#define CSR_HPMCOUNTER29 0xc1d
+#define CSR_HPMCOUNTER30 0xc1e
+#define CSR_HPMCOUNTER31 0xc1f
#define CSR_CYCLEH 0xc80
#define CSR_TIMEH 0xc81
#define CSR_INSTRETH 0xc82
+#define CSR_HPMCOUNTER3H 0xc83
+#define CSR_HPMCOUNTER4H 0xc84
+#define CSR_HPMCOUNTER5H 0xc85
+#define CSR_HPMCOUNTER6H 0xc86
+#define CSR_HPMCOUNTER7H 0xc87
+#define CSR_HPMCOUNTER8H 0xc88
+#define CSR_HPMCOUNTER9H 0xc89
+#define CSR_HPMCOUNTER10H 0xc8a
+#define CSR_HPMCOUNTER11H 0xc8b
+#define CSR_HPMCOUNTER12H 0xc8c
+#define CSR_HPMCOUNTER13H 0xc8d
+#define CSR_HPMCOUNTER14H 0xc8e
+#define CSR_HPMCOUNTER15H 0xc8f
+#define CSR_HPMCOUNTER16H 0xc90
+#define CSR_HPMCOUNTER17H 0xc91
+#define CSR_HPMCOUNTER18H 0xc92
+#define CSR_HPMCOUNTER19H 0xc93
+#define CSR_HPMCOUNTER20H 0xc94
+#define CSR_HPMCOUNTER21H 0xc95
+#define CSR_HPMCOUNTER22H 0xc96
+#define CSR_HPMCOUNTER23H 0xc97
+#define CSR_HPMCOUNTER24H 0xc98
+#define CSR_HPMCOUNTER25H 0xc99
+#define CSR_HPMCOUNTER26H 0xc9a
+#define CSR_HPMCOUNTER27H 0xc9b
+#define CSR_HPMCOUNTER28H 0xc9c
+#define CSR_HPMCOUNTER29H 0xc9d
+#define CSR_HPMCOUNTER30H 0xc9e
+#define CSR_HPMCOUNTER31H 0xc9f
#define CSR_SSTATUS 0x100
#define CSR_SIE 0x104
--
2.30.2
next prev parent reply other threads:[~2022-02-19 0:47 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-02-19 0:46 [v6 0/9] Improve RISC-V Perf support using SBI PMU and sscofpmf extension Atish Patra
2022-02-19 0:46 ` [v6 1/9] RISC-V: Remove the current perf implementation Atish Patra
2022-02-19 0:46 ` Atish Patra [this message]
2022-02-19 0:46 ` [v6 3/9] RISC-V: Add a perf core library for pmu drivers Atish Patra
2022-02-19 0:46 ` [v6 4/9] RISC-V: Add a simple platform driver for RISC-V legacy perf Atish Patra
2022-02-19 0:46 ` [v6 5/9] RISC-V: Add RISC-V SBI PMU extension definitions Atish Patra
2022-02-19 0:46 ` [v6 6/9] RISC-V: Add perf platform driver based on SBI PMU extension Atish Patra
2022-02-19 0:46 ` [v6 7/9] RISC-V: Add sscofpmf extension support Atish Patra
2022-02-19 0:46 ` [v6 8/9] Documentation: riscv: Remove the old documentation Atish Patra
2022-02-19 0:47 ` [v6 9/9] MAINTAINERS: Add entry for RISC-V PMU drivers Atish Patra
2022-03-12 7:51 ` [v6 0/9] Improve RISC-V Perf support using SBI PMU and sscofpmf extension Nikita Shubin
2022-03-21 23:57 ` Palmer Dabbelt
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