From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A4F20C4332F for ; Mon, 21 Feb 2022 15:02:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1378723AbiBUPCZ (ORCPT ); Mon, 21 Feb 2022 10:02:25 -0500 Received: from mxb-00190b01.gslb.pphosted.com ([23.128.96.19]:35156 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1378659AbiBUPCX (ORCPT ); Mon, 21 Feb 2022 10:02:23 -0500 X-Greylist: delayed 7320 seconds by postgrey-1.37 at lindbergh.monkeyblade.net; Mon, 21 Feb 2022 07:01:36 PST Received: from relay11.mail.gandi.net (relay11.mail.gandi.net [IPv6:2001:4b98:dc4:8::231]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CF6F7E0D; Mon, 21 Feb 2022 07:01:31 -0800 (PST) Received: (Authenticated sender: miquel.raynal@bootlin.com) by mail.gandi.net (Postfix) with ESMTPSA id 96541100015; Mon, 21 Feb 2022 15:01:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=bootlin.com; s=gm1; t=1645455686; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=hK8yaZhqzk1pLLQ0EIRdH5lQc4U08JDqPo1Cz+pstQU=; b=fxefFsnJtjw0wIlbRk3lkZrzOYrgPmEfqJGrdG+afxpHk3u087CAgCacd9BKOQ5ngMZBOo lRoJQsmNjW5MkMRiMtENwgxOTLFk9mllDeShWemKC+rsqzJPM2/AbyQ+4rTQRpfS4pF/yj yp/3qM/7AeuuRFQojwKJXITP5Jgf5gJXUeu7ckHU5z5HyKs550vki2xaqSPhfMQImwdGaL P4jG8WkEs5Kgd5eJuRjJvWr+knb10/Qf8d3F2SLFeYAbP0MWibPu34uZ4EAQKQUHnEmmgZ vR40cxTsDiZiNJE2yxersBJE306G1R3tmyTgG9yhKuw92onKE3kotNEKQtCZfw== Date: Mon, 21 Feb 2022 16:01:21 +0100 From: Miquel Raynal To: Geert Uytterhoeven Cc: Viresh Kumar , Andy Shevchenko , Vinod Koul , Geert Uytterhoeven , Magnus Damm , Michael Turquette , Stephen Boyd , Rob Herring , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , dmaengine , Linux-Renesas , linux-clk , Thomas Petazzoni , Milan Stevanovic , Jimmy Lalande , Laetitia MARIOTTINI Subject: Re: [PATCH 3/8] soc: renesas: rzn1-sysc: Export function to set dmamux Message-ID: <20220221160121.6a7a0ed6@xps13> In-Reply-To: References: <20220218181226.431098-1-miquel.raynal@bootlin.com> <20220218181226.431098-4-miquel.raynal@bootlin.com> Organization: Bootlin X-Mailer: Claws Mail 3.17.7 (GTK+ 2.24.32; x86_64-pc-linux-gnu) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: devicetree@vger.kernel.org Hi Geert, geert@linux-m68k.org wrote on Mon, 21 Feb 2022 10:16:24 +0100: > Hi Miquel, >=20 > On Fri, Feb 18, 2022 at 7:12 PM Miquel Raynal = wrote: > > The dmamux register is located within the system controller. > > > > Without syscon, we need an extra helper in order to give write access to > > this register to a dmamux driver. > > > > Signed-off-by: Miquel Raynal =20 >=20 > Thanks for your patch! >=20 > > --- a/drivers/clk/renesas/r9a06g032-clocks.c > > +++ b/drivers/clk/renesas/r9a06g032-clocks.c =20 >=20 > Missing #include >=20 > > @@ -315,6 +315,27 @@ struct r9a06g032_priv { > > void __iomem *reg; > > }; > > > > +/* Exported helper to access the DMAMUX register */ > > +static struct r9a06g032_priv *syscon_priv; =20 >=20 > I'd call this sysctrl_priv, as that matches the bindings and > binding header file name. Ok. >=20 > > +int r9a06g032_syscon_set_dmamux(u32 mask, u32 val) > > +{ > > + u32 dmamux; > > + > > + if (!syscon_priv) > > + return -EPROBE_DEFER; > > + > > + spin_lock(&syscon_priv->lock); =20 >=20 > This needs propection against interrupts =3D> spin_lock_irqsave(). Yes. >=20 > > + > > + dmamux =3D readl(syscon_priv->reg + R9A06G032_SYSCON_DMAMUX); > > + dmamux &=3D ~mask; > > + dmamux |=3D val & mask; > > + writel(dmamux, syscon_priv->reg + R9A06G032_SYSCON_DMAMUX); > > + > > + spin_unlock(&syscon_priv->lock); > > + > > + return 0; > > +} > > + > > /* register/bit pairs are encoded as an uint16_t */ > > static void > > clk_rdesc_set(struct r9a06g032_priv *clocks, =20 >=20 > > --- a/include/dt-bindings/clock/r9a06g032-sysctrl.h > > +++ b/include/dt-bindings/clock/r9a06g032-sysctrl.h > > @@ -145,4 +145,6 @@ > > #define R9A06G032_CLK_UART6 152 > > #define R9A06G032_CLK_UART7 153 > > > > +#define R9A06G032_SYSCON_DMAMUX 0xA0 =20 >=20 > I don't think this needs to be part of the bindings, so please move > it to the driver source file. I've moved it to the top of the file. There definitions are a bit mixed with the code, I don't like this, so I kept it at the top. >=20 > > --- /dev/null > > +++ b/include/linux/soc/renesas/r9a06g032-syscon.h =20 >=20 > r9a06g032-sysctrl.h etc. Done. >=20 > > @@ -0,0 +1,11 @@ > > +/* SPDX-License-Identifier: GPL-2.0 */ > > +#ifndef __LINUX_SOC_RENESAS_R9A06G032_SYSCON_H__ > > +#define __LINUX_SOC_RENESAS_R9A06G032_SYSCON_H__ > > + > > +#ifdef CONFIG_CLK_R9A06G032 > > +int r9a06g032_syscon_set_dmamux(u32 mask, u32 val); > > +#else > > +static inline int r9a06g032_syscon_set_dmamux(u32 mask, u32 val) { ret= urn -ENODEV; } > > +#endif > > + > > +#endif /* __LINUX_SOC_RENESAS_R9A06G032_SYSCON_H__ */ > > -- > > 2.27.0 =20 >=20 > Gr{oetje,eeting}s, >=20 > Geert >=20 > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m6= 8k.org >=20 > In personal conversations with technical people, I call myself a hacker. = But > when I'm talking to journalists I just say "programmer" or something like= that. > -- Linus Torvalds Thanks, Miqu=C3=A8l