* [PATCH 0/2] DSS: Add support for DisplayPort @ 2022-02-22 16:32 Rahul T R 2022-02-22 16:32 ` [PATCH 1/2] arm64: dts: ti: k3-j721e-main: add DP & DP PHY Rahul T R 2022-02-22 16:32 ` [PATCH 2/2] arm64: dts: ti: k3-j721e-common-proc-board: add DP to j7 evm Rahul T R 0 siblings, 2 replies; 6+ messages in thread From: Rahul T R @ 2022-02-22 16:32 UTC (permalink / raw) To: nm Cc: vigneshr, kristo, robh+dt, krzysztof.kozlowski, linux-arm-kernel, devicetree, linux-kernel, tomi.valkeinen, laurent.pinchart The following series of patches enables DisplayPort on j721e-evm Tomi Valkeinen (2): arm64: dts: ti: k3-j721e-main: add DP & DP PHY arm64: dts: ti: k3-j721e-common-proc-board: add DP to j7 evm .../dts/ti/k3-j721e-common-proc-board.dts | 66 +++++++++++- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 102 ++++++++++++++++++ 2 files changed, 164 insertions(+), 4 deletions(-) -- 2.17.1 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 1/2] arm64: dts: ti: k3-j721e-main: add DP & DP PHY 2022-02-22 16:32 [PATCH 0/2] DSS: Add support for DisplayPort Rahul T R @ 2022-02-22 16:32 ` Rahul T R 2022-02-28 4:17 ` Kishon Vijay Abraham I 2022-02-22 16:32 ` [PATCH 2/2] arm64: dts: ti: k3-j721e-common-proc-board: add DP to j7 evm Rahul T R 1 sibling, 1 reply; 6+ messages in thread From: Rahul T R @ 2022-02-22 16:32 UTC (permalink / raw) To: nm Cc: vigneshr, kristo, robh+dt, krzysztof.kozlowski, linux-arm-kernel, devicetree, linux-kernel, tomi.valkeinen, laurent.pinchart From: Tomi Valkeinen <tomi.valkeinen@ti.com> Add DT nodes for DisplayPort and DisplayPort PHY. The DP is Cadence MHDP 8546 and the PHY is a Cadence Torrent PHY with TI WIZ wrapper. A slight irregularity in the bindings is the DPTX PHY register block, which is in the MHDP IP, but is needed and mapped by the PHY. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Rahul T R <r-ravikumar@ti.com> --- arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 102 ++++++++++++++++++++++ 1 file changed, 102 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi index 599861259a30..9e2b212100bb 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi @@ -786,6 +786,82 @@ #size-cells = <2>; }; + serdes_wiz4: wiz@5050000 { + compatible = "ti,j721e-wiz-10g"; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>; + clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&cmn_refclk>; + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; + assigned-clocks = <&k3_clks 297 9>; + assigned-clock-parents = <&k3_clks 297 10>; + assigned-clock-rates = <19200000>; + num-lanes = <4>; + #reset-cells = <1>; + ranges = <0x5050000 0x0 0x5050000 0x10000>, + <0xa030a00 0x0 0xa030a00 0x40>; + + wiz4_pll0_refclk: pll0-refclk { + clocks = <&k3_clks 297 9>, <&cmn_refclk>; + clock-output-names = "wiz4_pll0_refclk"; + #clock-cells = <0>; + assigned-clocks = <&wiz4_pll0_refclk>; + assigned-clock-parents = <&k3_clks 297 9>; + }; + + wiz4_pll1_refclk: pll1-refclk { + clocks = <&k3_clks 297 9>, <&cmn_refclk>; + clock-output-names = "wiz4_pll1_refclk"; + #clock-cells = <0>; + assigned-clocks = <&wiz4_pll1_refclk>; + assigned-clock-parents = <&k3_clks 297 9>; + }; + + wiz4_refclk_dig: refclk-dig { + clocks = <&k3_clks 297 9>, <&cmn_refclk>; + clock-output-names = "wiz4_refclk_dig"; + #clock-cells = <0>; + assigned-clocks = <&wiz4_refclk_dig>; + assigned-clock-parents = <&k3_clks 297 9>; + }; + + wiz4_cmn_refclk_dig_div: cmn-refclk-dig-div { + clocks = <&wiz4_refclk_dig>; + #clock-cells = <0>; + }; + + wiz4_cmn_refclk1_dig_div: cmn-refclk1-dig-div { + clocks = <&wiz4_pll1_refclk>; + #clock-cells = <0>; + }; + + serdes4: serdes@5050000 { + /* + * Note: we also map DPTX PHY registers as the Torrent + * needs to manage those. + */ + compatible = "ti,j721e-serdes-10g"; + reg = <0x5050000 0x10000>, + <0xa030a00 0x40>; /* DPTX PHY */ + reg-names = "torrent_phy", "dptx_phy"; + + resets = <&serdes_wiz4 0>; + reset-names = "torrent_reset"; + clocks = <&wiz4_pll0_refclk>; + clock-names = "refclk"; + #address-cells = <1>; + #size-cells = <0>; + torrent_phy_dp: phy@0 { + reg = <0>; + resets = <&serdes_wiz4 1>; + cdns,phy-type = <PHY_TYPE_DP>; + cdns,num-lanes = <4>; + cdns,max-bit-rate = <5400>; + #phy-cells = <0>; + }; + }; + }; + main_uart0: serial@2800000 { compatible = "ti,j721e-uart", "ti,am654-uart"; reg = <0x00 0x02800000 0x00 0x100>; @@ -1264,6 +1340,32 @@ }; }; + mhdp: dp-bridge@a000000 { + compatible = "ti,j721e-mhdp8546"; + /* + * Note: we do not map DPTX PHY area, as that is handled by + * the PHY driver. + */ + reg = <0x0 0xa000000 0x0 0x30a00>, /* DSS_EDP0_V2A_CORE_VP_REGS_APB */ + <0x0 0x4f40000 0x0 0x20>; /* DSS_EDP0_INTG_CFG_VP */ + reg-names = "mhdptx", "j721e-intg"; + + clocks = <&k3_clks 151 36>; + + phys = <&torrent_phy_dp>; + phy-names = "dpphy"; + + interrupt-parent = <&gic500>; + interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>; + + power-domains = <&k3_pds 151 TI_SCI_PD_EXCLUSIVE>; + + dp0_ports: ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + dss: dss@4a00000 { compatible = "ti,j721e-dss"; reg = -- 2.17.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] arm64: dts: ti: k3-j721e-main: add DP & DP PHY 2022-02-22 16:32 ` [PATCH 1/2] arm64: dts: ti: k3-j721e-main: add DP & DP PHY Rahul T R @ 2022-02-28 4:17 ` Kishon Vijay Abraham I 2022-03-31 14:15 ` Rahul T R 0 siblings, 1 reply; 6+ messages in thread From: Kishon Vijay Abraham I @ 2022-02-28 4:17 UTC (permalink / raw) To: Rahul T R, nm Cc: vigneshr, kristo, robh+dt, krzysztof.kozlowski, linux-arm-kernel, devicetree, linux-kernel, tomi.valkeinen, laurent.pinchart Hi Rahul, On 22/02/22 10:02 pm, Rahul T R wrote: > From: Tomi Valkeinen <tomi.valkeinen@ti.com> > > Add DT nodes for DisplayPort and DisplayPort PHY. The DP is Cadence MHDP > 8546 and the PHY is a Cadence Torrent PHY with TI WIZ wrapper. > > A slight irregularity in the bindings is the DPTX PHY register block, > which is in the MHDP IP, but is needed and mapped by the PHY. > > Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> > Signed-off-by: Rahul T R <r-ravikumar@ti.com> > --- > arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 102 ++++++++++++++++++++++ > 1 file changed, 102 insertions(+) > > diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi > index 599861259a30..9e2b212100bb 100644 > --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi > +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi > @@ -786,6 +786,82 @@ > #size-cells = <2>; > }; > > + serdes_wiz4: wiz@5050000 { > + compatible = "ti,j721e-wiz-10g"; > + #address-cells = <1>; > + #size-cells = <1>; > + power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>; > + clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&cmn_refclk>; > + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; > + assigned-clocks = <&k3_clks 297 9>; > + assigned-clock-parents = <&k3_clks 297 10>; > + assigned-clock-rates = <19200000>; > + num-lanes = <4>; > + #reset-cells = <1>; > + ranges = <0x5050000 0x0 0x5050000 0x10000>, > + <0xa030a00 0x0 0xa030a00 0x40>; > + > + wiz4_pll0_refclk: pll0-refclk { > + clocks = <&k3_clks 297 9>, <&cmn_refclk>; > + clock-output-names = "wiz4_pll0_refclk"; > + #clock-cells = <0>; > + assigned-clocks = <&wiz4_pll0_refclk>; > + assigned-clock-parents = <&k3_clks 297 9>; > + }; > + > + wiz4_pll1_refclk: pll1-refclk { > + clocks = <&k3_clks 297 9>, <&cmn_refclk>; > + clock-output-names = "wiz4_pll1_refclk"; > + #clock-cells = <0>; > + assigned-clocks = <&wiz4_pll1_refclk>; > + assigned-clock-parents = <&k3_clks 297 9>; > + }; > + > + wiz4_refclk_dig: refclk-dig { > + clocks = <&k3_clks 297 9>, <&cmn_refclk>; > + clock-output-names = "wiz4_refclk_dig"; > + #clock-cells = <0>; > + assigned-clocks = <&wiz4_refclk_dig>; > + assigned-clock-parents = <&k3_clks 297 9>; > + }; > + > + wiz4_cmn_refclk_dig_div: cmn-refclk-dig-div { > + clocks = <&wiz4_refclk_dig>; > + #clock-cells = <0>; > + }; > + > + wiz4_cmn_refclk1_dig_div: cmn-refclk1-dig-div { > + clocks = <&wiz4_pll1_refclk>; > + #clock-cells = <0>; > + }; I'd prefer we deprecate creating clock sub-nodes for new platform additions and use a similar approach as that used for AM64 (use phandle with a parameter to refer clocks). Please refer how this was created for AM64 https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/ti/k3-am64-main.dtsi#n795 Since this is the same SERDES IP as used in AM64, you should be able to use the same DT binding as that used in AM64. But if you'd like to adapt "ti,j721e-wiz-10g" to use phandle with parameter in the WIZ driver (while making sure the existing sub-node based binding is not broken), that is highly welcomed. > + > + serdes4: serdes@5050000 { > + /* > + * Note: we also map DPTX PHY registers as the Torrent > + * needs to manage those. > + */ > + compatible = "ti,j721e-serdes-10g"; > + reg = <0x5050000 0x10000>, > + <0xa030a00 0x40>; /* DPTX PHY */ > + reg-names = "torrent_phy", "dptx_phy"; > + > + resets = <&serdes_wiz4 0>; > + reset-names = "torrent_reset"; > + clocks = <&wiz4_pll0_refclk>; > + clock-names = "refclk"; > + #address-cells = <1>; > + #size-cells = <0>; > + torrent_phy_dp: phy@0 { > + reg = <0>; > + resets = <&serdes_wiz4 1>; > + cdns,phy-type = <PHY_TYPE_DP>; > + cdns,num-lanes = <4>; > + cdns,max-bit-rate = <5400>; > + #phy-cells = <0>; > + }; The link sub-nodes should be in the board DTS file. Thanks, Kishon ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 1/2] arm64: dts: ti: k3-j721e-main: add DP & DP PHY 2022-02-28 4:17 ` Kishon Vijay Abraham I @ 2022-03-31 14:15 ` Rahul T R 0 siblings, 0 replies; 6+ messages in thread From: Rahul T R @ 2022-03-31 14:15 UTC (permalink / raw) To: Kishon Vijay Abraham I Cc: nm, vigneshr, kristo, robh+dt, krzysztof.kozlowski, linux-arm-kernel, devicetree, linux-kernel, tomi.valkeinen, laurent.pinchart On 09:47-20220228, Kishon Vijay Abraham I wrote: > Hi Rahul, > > On 22/02/22 10:02 pm, Rahul T R wrote: > > From: Tomi Valkeinen <tomi.valkeinen@ti.com> > > > > Add DT nodes for DisplayPort and DisplayPort PHY. The DP is Cadence MHDP > > 8546 and the PHY is a Cadence Torrent PHY with TI WIZ wrapper. > > > > A slight irregularity in the bindings is the DPTX PHY register block, > > which is in the MHDP IP, but is needed and mapped by the PHY. > > > > Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> > > Signed-off-by: Rahul T R <r-ravikumar@ti.com> > > --- > > arch/arm64/boot/dts/ti/k3-j721e-main.dtsi | 102 ++++++++++++++++++++++ > > 1 file changed, 102 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi > > index 599861259a30..9e2b212100bb 100644 > > --- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi > > +++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi > > @@ -786,6 +786,82 @@ > > #size-cells = <2>; > > }; > > > > + serdes_wiz4: wiz@5050000 { > > + compatible = "ti,j721e-wiz-10g"; > > + #address-cells = <1>; > > + #size-cells = <1>; > > + power-domains = <&k3_pds 297 TI_SCI_PD_EXCLUSIVE>; > > + clocks = <&k3_clks 297 1>, <&k3_clks 297 9>, <&cmn_refclk>; > > + clock-names = "fck", "core_ref_clk", "ext_ref_clk"; > > + assigned-clocks = <&k3_clks 297 9>; > > + assigned-clock-parents = <&k3_clks 297 10>; > > + assigned-clock-rates = <19200000>; > > + num-lanes = <4>; > > + #reset-cells = <1>; > > + ranges = <0x5050000 0x0 0x5050000 0x10000>, > > + <0xa030a00 0x0 0xa030a00 0x40>; > > + > > + wiz4_pll0_refclk: pll0-refclk { > > + clocks = <&k3_clks 297 9>, <&cmn_refclk>; > > + clock-output-names = "wiz4_pll0_refclk"; > > + #clock-cells = <0>; > > + assigned-clocks = <&wiz4_pll0_refclk>; > > + assigned-clock-parents = <&k3_clks 297 9>; > > + }; > > + > > + wiz4_pll1_refclk: pll1-refclk { > > + clocks = <&k3_clks 297 9>, <&cmn_refclk>; > > + clock-output-names = "wiz4_pll1_refclk"; > > + #clock-cells = <0>; > > + assigned-clocks = <&wiz4_pll1_refclk>; > > + assigned-clock-parents = <&k3_clks 297 9>; > > + }; > > + > > + wiz4_refclk_dig: refclk-dig { > > + clocks = <&k3_clks 297 9>, <&cmn_refclk>; > > + clock-output-names = "wiz4_refclk_dig"; > > + #clock-cells = <0>; > > + assigned-clocks = <&wiz4_refclk_dig>; > > + assigned-clock-parents = <&k3_clks 297 9>; > > + }; > > + > > + wiz4_cmn_refclk_dig_div: cmn-refclk-dig-div { > > + clocks = <&wiz4_refclk_dig>; > > + #clock-cells = <0>; > > + }; > > + > > + wiz4_cmn_refclk1_dig_div: cmn-refclk1-dig-div { > > + clocks = <&wiz4_pll1_refclk>; > > + #clock-cells = <0>; > > + }; > > I'd prefer we deprecate creating clock sub-nodes for new platform additions and > use a similar approach as that used for AM64 (use phandle with a parameter to > refer clocks). Please refer how this was created for AM64 > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/arm64/boot/dts/ti/k3-am64-main.dtsi#n795 > > Since this is the same SERDES IP as used in AM64, you should be able to use the > same DT binding as that used in AM64. But if you'd like to adapt > "ti,j721e-wiz-10g" to use phandle with parameter in the WIZ driver (while making > sure the existing sub-node based binding is not broken), that is highly welcomed. > Thanks Kishon, Will address this in the respin Regards Rahul T R > > + > > + serdes4: serdes@5050000 { > > + /* > > + * Note: we also map DPTX PHY registers as the Torrent > > + * needs to manage those. > > + */ > > + compatible = "ti,j721e-serdes-10g"; > > + reg = <0x5050000 0x10000>, > > + <0xa030a00 0x40>; /* DPTX PHY */ > > + reg-names = "torrent_phy", "dptx_phy"; > > + > > + resets = <&serdes_wiz4 0>; > > + reset-names = "torrent_reset"; > > + clocks = <&wiz4_pll0_refclk>; > > + clock-names = "refclk"; > > + #address-cells = <1>; > > + #size-cells = <0>; > > + torrent_phy_dp: phy@0 { > > + reg = <0>; > > + resets = <&serdes_wiz4 1>; > > + cdns,phy-type = <PHY_TYPE_DP>; > > + cdns,num-lanes = <4>; > > + cdns,max-bit-rate = <5400>; > > + #phy-cells = <0>; > > + }; > > The link sub-nodes should be in the board DTS file. > > Thanks, > Kishon ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH 2/2] arm64: dts: ti: k3-j721e-common-proc-board: add DP to j7 evm 2022-02-22 16:32 [PATCH 0/2] DSS: Add support for DisplayPort Rahul T R 2022-02-22 16:32 ` [PATCH 1/2] arm64: dts: ti: k3-j721e-main: add DP & DP PHY Rahul T R @ 2022-02-22 16:32 ` Rahul T R 2022-03-11 8:44 ` Tomi Valkeinen 1 sibling, 1 reply; 6+ messages in thread From: Rahul T R @ 2022-02-22 16:32 UTC (permalink / raw) To: nm Cc: vigneshr, kristo, robh+dt, krzysztof.kozlowski, linux-arm-kernel, devicetree, linux-kernel, tomi.valkeinen, laurent.pinchart From: Tomi Valkeinen <tomi.valkeinen@ti.com> Add the endpoint nodes to describe connection from DSS => MHDP => DisplayPort connector. Also add the required pinmux nodes for hotplug. Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> Signed-off-by: Rahul T R <r-ravikumar@ti.com> --- .../dts/ti/k3-j721e-common-proc-board.dts | 66 +++++++++++++++++-- 1 file changed, 62 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 2d7596911b27..fe20c193f299 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -148,6 +148,28 @@ pinctrl-0 = <&main_mcan2_gpio_pins_default>; standby-gpios = <&main_gpio0 127 GPIO_ACTIVE_HIGH>; }; + + dp_pwr_3v3: fixedregulator-dp-prw { + compatible = "regulator-fixed"; + regulator-name = "dp-pwr"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&exp4 0 0>; /* P0 - DP0_PWR_SW_EN */ + enable-active-high; + }; + + dp0: connector { + compatible = "dp-connector"; + label = "DP0"; + type = "full-size"; + dp-pwr-supply = <&dp_pwr_3v3>; + + port { + dp_connector_in: endpoint { + remote-endpoint = <&dp0_out>; + }; + }; + }; }; &main_pmx0 { @@ -190,6 +212,12 @@ >; }; + dp0_pins_default: dp0-pins-default { + pinctrl-single,pins = < + J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */ + >; + }; + main_i2c1_exp4_pins_default: main-i2c1-exp4-pins-default { pinctrl-single,pins = < J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */ @@ -660,6 +688,40 @@ <&k3_clks 152 18>; /* PLL23_HSDIV0 */ }; +&dss_ports { + port@0 { + reg = <0>; + + dpi0_out: endpoint { + remote-endpoint = <&dp0_in>; + }; + }; +}; + +&mhdp { + pinctrl-names = "default"; + pinctrl-0 = <&dp0_pins_default>; +}; + +&dp0_ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dp0_in: endpoint { + remote-endpoint = <&dpi0_out>; + }; + }; + + port@4 { + reg = <4>; + dp0_out: endpoint { + remote-endpoint = <&dp_connector_in>; + }; + }; +}; + &mcasp0 { status = "disabled"; }; @@ -845,10 +907,6 @@ status = "disabled"; }; -&dss { - status = "disabled"; -}; - &icssg0_mdio { status = "disabled"; }; -- 2.17.1 ^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH 2/2] arm64: dts: ti: k3-j721e-common-proc-board: add DP to j7 evm 2022-02-22 16:32 ` [PATCH 2/2] arm64: dts: ti: k3-j721e-common-proc-board: add DP to j7 evm Rahul T R @ 2022-03-11 8:44 ` Tomi Valkeinen 0 siblings, 0 replies; 6+ messages in thread From: Tomi Valkeinen @ 2022-03-11 8:44 UTC (permalink / raw) To: Rahul T R, nm Cc: vigneshr, kristo, robh+dt, krzysztof.kozlowski, linux-arm-kernel, devicetree, linux-kernel, laurent.pinchart On 22/02/2022 18:32, Rahul T R wrote: > From: Tomi Valkeinen <tomi.valkeinen@ti.com> > > Add the endpoint nodes to describe connection from > DSS => MHDP => DisplayPort connector. > Also add the required pinmux nodes for hotplug. > > Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com> > Signed-off-by: Rahul T R <r-ravikumar@ti.com> > --- > .../dts/ti/k3-j721e-common-proc-board.dts | 66 +++++++++++++++++-- > 1 file changed, 62 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts > index 2d7596911b27..fe20c193f299 100644 > --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts > +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts > @@ -148,6 +148,28 @@ > pinctrl-0 = <&main_mcan2_gpio_pins_default>; > standby-gpios = <&main_gpio0 127 GPIO_ACTIVE_HIGH>; > }; > + > + dp_pwr_3v3: fixedregulator-dp-prw { > + compatible = "regulator-fixed"; > + regulator-name = "dp-pwr"; > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + gpio = <&exp4 0 0>; /* P0 - DP0_PWR_SW_EN */ > + enable-active-high; > + }; > + > + dp0: connector { > + compatible = "dp-connector"; > + label = "DP0"; > + type = "full-size"; > + dp-pwr-supply = <&dp_pwr_3v3>; > + > + port { > + dp_connector_in: endpoint { > + remote-endpoint = <&dp0_out>; > + }; > + }; > + }; > }; > > &main_pmx0 { > @@ -190,6 +212,12 @@ > >; > }; > > + dp0_pins_default: dp0-pins-default { > + pinctrl-single,pins = < > + J721E_IOPAD(0x1c4, PIN_INPUT, 5) /* SPI0_CS1.DP0_HPD */ > + >; > + }; > + > main_i2c1_exp4_pins_default: main-i2c1-exp4-pins-default { > pinctrl-single,pins = < > J721E_IOPAD(0x230, PIN_INPUT, 7) /* (U2) ECAP0_IN_APWM_OUT.GPIO1_11 */ > @@ -660,6 +688,40 @@ > <&k3_clks 152 18>; /* PLL23_HSDIV0 */ > }; > > +&dss_ports { > + port@0 { > + reg = <0>; > + > + dpi0_out: endpoint { > + remote-endpoint = <&dp0_in>; > + }; > + }; > +}; > + > +&mhdp { > + pinctrl-names = "default"; > + pinctrl-0 = <&dp0_pins_default>; > +}; > + > +&dp0_ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@0 { > + reg = <0>; > + dp0_in: endpoint { > + remote-endpoint = <&dpi0_out>; > + }; > + }; > + > + port@4 { > + reg = <4>; > + dp0_out: endpoint { > + remote-endpoint = <&dp_connector_in>; > + }; > + }; > +}; > + > &mcasp0 { > status = "disabled"; > }; > @@ -845,10 +907,6 @@ > status = "disabled"; > }; > > -&dss { > - status = "disabled"; > -}; > - > &icssg0_mdio { > status = "disabled"; > }; Reviewed-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Tomi ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-03-31 14:15 UTC | newest] Thread overview: 6+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-02-22 16:32 [PATCH 0/2] DSS: Add support for DisplayPort Rahul T R 2022-02-22 16:32 ` [PATCH 1/2] arm64: dts: ti: k3-j721e-main: add DP & DP PHY Rahul T R 2022-02-28 4:17 ` Kishon Vijay Abraham I 2022-03-31 14:15 ` Rahul T R 2022-02-22 16:32 ` [PATCH 2/2] arm64: dts: ti: k3-j721e-common-proc-board: add DP to j7 evm Rahul T R 2022-03-11 8:44 ` Tomi Valkeinen
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